MC68HRC98JK3ECDW Freescale Semiconductor, MC68HRC98JK3ECDW Datasheet - Page 115
![IC MCU 4K FLASH 8MHZ 20-SOIC](/photos/6/50/65027/375-20-soic_sml.jpg)
MC68HRC98JK3ECDW
Manufacturer Part Number
MC68HRC98JK3ECDW
Description
IC MCU 4K FLASH 8MHZ 20-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JK1ECDWE.pdf
(180 pages)
Specifications of MC68HRC98JK3ECDW
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
15
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HRC98JK3ECDW
Manufacturer:
MOTOROLA
Quantity:
2 880
Part Number:
MC68HRC98JK3ECDW
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
11.3.1 IRQ Pin
A zero on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or
reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set,
both of the following actions must occur to clear IRQ:
The vector fetch or software clear and the return of the IRQ pin to logic one may occur in any order. The
interrupt request remains pending as long as the IRQ pin is at logic zero. A reset will clear the latch and
the MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or
software clear immediately clears the IRQ latch.
The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not
affected by the IMASK bit, which makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
11.4 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ latch can be cleared during the break
state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during
the break state. (See
To allow software to clear the IRQ latch during a break interrupt, write a one to the BCFE bit. If a latch is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a zero to the BCFE bit. With BCFE at zero (its default
state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on
the IRQ latch.
Freescale Semiconductor
•
•
Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a logic one to the ACK
bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that
poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving
an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does
not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK
bit latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the
program counter with the vector address at locations $FFFA and $FFFB.
Return of the IRQ pin to logic one — As long as the IRQ pin is at logic zero, IRQ remains active.
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
An internal pull-up resistor to V
disabled by setting the IRQPUD bit in the CONFIG2 register ($001E).
Chapter 5 System Integration Module
MC68HC908JL3E Family Data Sheet, Rev. 4
DD
NOTE
NOTE
is connected to the IRQ pin; this can be
(SIM).)
IRQ Module During Break Interrupts
115