MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet

no-image

MC908AZ32ACFU

Manufacturer Part Number
MC908AZ32ACFU
Description
IC MCU 32K FLASH 8.4MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908AZ32ACFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
40
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
MC68HC908AZ32A
Data Sheet
M68HC08
Microcontrollers
MC68HC908AZ32A
Rev. 2
10/2005
freescale.com

MC908AZ32ACFU Summary of contents

Page 1

MC68HC908AZ32A Data Sheet M68HC08 Microcontrollers MC68HC908AZ32A Rev. 2 10/2005 freescale.com ...

Page 2

...

Page 3

... Chapter 26 Revision History convenience, the page number designators have been linked to the appropriate location. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2006. All rights reserved. ...

Page 4

... MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 5

... Chapter 19 Timer Interface Module B (TIMB 207 Chapter 20 Programmable Interrupt Timer (PIT 223 Chapter 21 Analog-To-Digital Converter (ADC-15 .229 Chapter 22 Keyboard Module (KBD 237 Chapter 23 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Chapter 24 MSCAN Controller (MSCAN08 263 Chapter 25 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Chapter 26 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Freescale Semiconductor MC68HC908AZ32A Data Sheet, Rev ...

Page 6

... List of Paragraphs 6 MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 7

... CAN Receive Pin (CANRx 1.5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3 Additional Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4 Vector Addresses and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Freescale Semiconductor Chapter 1 General Description and DDA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SSA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DDAREF / REFL ) ...

Page 8

... Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.2 Features 6.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8 Chapter 4 Flash Memory Chapter 5 EEPROM Chapter 6 Central Processor Unit (CPU) MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 9

... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.2 Features 8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.3.1 Crystal Oscillator Circuit 8.3.2 Phase-Locked Loop Circuit (PLL 8.3.3 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.3.4 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Freescale Semiconductor Chapter 7 System Integration Module (SIM) Chapter 8 Clock Generator Module (CGM) MC68HC908AZ32A Data Sheet, Rev ...

Page 10

... DDA Chapter 9 Configuration Register (CONFIG-1) Chapter 10 Configuration Register (CONFIG-2) Chapter 11 Brake Module MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 11

... Features 129 14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 14.3.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 14.3.2 Forced Reset Operation 130 14.3.3 False Reset Protection 130 Freescale Semiconductor Chapter 12 Monitor ROM (MON) Chapter 13 Computer Operating Properly (COP Chapter 14 Low Voltage Inhibit (LVI) MC68HC908AZ32A Data Sheet, Rev ...

Page 12

... SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 16.8.7 SCI Baud Rate Register 162 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 17.2 Features 165 17.3 Pin Name and Register Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12 Chapter 15 External Interrupt Module (IRQ1) Chapter 16 Chapter 17 Serial Peirpheral Interface (SPI) MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 13

... Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 18.6 TIMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 18.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 18.7.1 TIMA Clock Pin (PTD6/ATD14/TACLK 196 18.7.2 TIMA Channel I/O Pins (PTF3/TCH5–PTF0/TCH2 and PTE3/TCH1–PTE2/TCH0 196 Freescale Semiconductor Chapter 18 Timer Interface Module A (TIMA) MC68HC908AZ32A Data Sheet, Rev ...

Page 14

... PIT During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 20.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 20.7.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 20.7.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 20.7.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 14 Chapter 19 Timer Interface Module B (TIMB) Chapter 20 Programmable Interrupt Timer (PIT) MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 15

... Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 23.2.2 Data Direction Register 244 23.3 Port 246 23.3.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 23.3.2 Data Direction Register 246 Freescale Semiconductor Chapter 21 )/ADC Voltage Reference Pin (V DDAREF )/ADC Voltage Reference Low Pin (V SSA Chapter 22 Keyboard Module (KBD) Chapter 23 I/O Ports MC68HC908AZ32A Data Sheet, Rev ...

Page 16

... Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 24.10 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 24.11 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 24.12 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 24.12.1 Message Buffer Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 24.12.2 Identifier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 24.12.3 Data Length Register (DLR 280 16 Chapter 24 MSCAN Controller (MSCAN08) MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 17

... EEPROM Memory Characteristics 306 25.1.14 FLASH Memory Characteristics 307 25.2 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 26.1 Major Changes Between Revision 2.0 and Revision 1 311 26.2 Major Changes Between Revision 1.0 and Revision 0 311 Freescale Semiconductor Chapter 25 Electrical Specifications Chapter 26 Revision History Glossary MC68HC908AZ32A Data Sheet, Rev ...

Page 18

... Table of Contents 18 MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 19

... Low-Power Design (Fully Static with Stop and Wait Modes) • Master Reset Pin and Power-On Reset • 5-Bit Keyboard Interrupt Module • MSCAN Controller (Scalable CAN) implements CAN 2.0b Protocol as Defined in BOSCH Specification September 1991 Freescale Semiconductor MC68HC908AZ32A Data Sheet, Rev ...

Page 20

... Memory-to-Memory Data Transfers Fast 8 × 8 Multiply Instruction • • Fast 16/8 Divide Instruction • Binary-Coded Decimal (BCD) Instructions • Optimization for Controller Applications • C Language Support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908AZ32A. 20 MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 21

M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 62 BYTES USER FLASH — 32,256 BYTES USER RAM —1024 BYTES USER EEPROM — 512 BYTES MONITOR ROM — 320 BYTES USER FLASH VECTOR SPACE — 52 BYTES ...

Page 22

... Figure 1-2. MC68HC908AZ32A 64 QFP Pin Assignments The following pin descriptions are just a quick reference. For a more detailed representation, see 22 NOTE Chapter 23 I/O Ports. MC68HC908AZ32A Data Sheet, Rev. 2 PTH0/KBD3 48 PTD3/ATD11 47 PTD2/ATD10 REFL V 44 DDAREF PTD1/ATD9 43 PTD0/ATD8 42 PTB7/ATD7 41 PTB6/ATD6 40 PTB5/ATD5 39 PTB4/ATD4 38 PTB3/ATD3 37 PTB2/ATD2 36 PTB1/ATD1 35 PTB0/ATD0 34 PTA7 33 Freescale Semiconductor ...

Page 23

... External Interrupt Pin (IRQ) IRQ is an asynchronous external interrupt pin. See 1.4.5 Analog Power Supply Pin ( the power supply pin for the analog portion of the Clock Generator Module (CGM). See DDA Chapter 8 Clock Generator Module Freescale Semiconductor and MCU 0.1 μ ...

Page 24

... SSA (CGM). (CGM). ) DDAREF (ADC-15 REFL Chapter 21 Analog-To-Digital Converter ) REFH and Chapter 23 I/O Chapter 18 Timer Interface Module A Chapter 16 Serial Communications Interface MC68HC908AZ32A Data Sheet, Rev. 2 (ADC-15). Chapter 21 Chapter 23 I/O Ports. Ports. (TIMA), Chapter 19 Timer and Chapter 23 I/O (SCI), Freescale Semiconductor Ports. ...

Page 25

... ADC Channel/Timer External Input Clock PTD5/ATD13 ADC Channel PTD4/ATD12/T BCLK ADC Channel ADC Channel/Timer External Input Clock PTD3/ATD11–PTD0/ ATD8 ADC Channels PTE7/SPSCK PTE6/MOSI Freescale Semiconductor (SPI), Chapter 18 Timer Interface Module A (TIMB), and Chapter 23 I/O and Chapter 23 I/O Ports. and Chapter 23 I/O Ports ...

Page 26

... Input Hi-Z Dual State Yes Input Hi-Z N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Input Hi-Z N/A N/A Output N/A N/A N/A N/A N/A Input Hi-Z N/A N/A Output Low Freescale Semiconductor ...

Page 27

... SPI SCI TIMA TIMB PIT SIM IRQ BRK LVI CGM Freescale Semiconductor Function CAN Serial Input CAN Serial Output Description Buffered version of OSC1 from Clock Generation Module (CGM) PLL-based or OSC1-based clock output from Clock Generator Module (CGM) CGMOUT divided by two SPI serial clock ...

Page 28

... This section contains instructions for ordering the MC68HC908AZ32A. 1.5.1 MC Order Numbers MC Order Number MC68HC908AZ32ACFU (64-Pin QFP) MC68HC908AZ32AVFU (64-Pin QFP) MC68HC908AZ32AMFU (64-Pin QFP) 28 Table 1-4. MC Order Numbers Temperature Range MC68HC908AZ32A Data Sheet, Rev. 2 Operating ° ° – ° ° – 105 C ° ° – 125 C Freescale Semiconductor ...

Page 29

... Freescale Semiconductor Chapter 7 System Integration Module I/O REGISTERS (80 BYTES) RAM (1024 BYTES) UNIMPLEMENTED (176 BYTES) CAN CONTROL AND MESSAGE BUFFERS (128 BYTES) UNIMPLEMENTED (640 BYTES) EEPROM (512 BYTES) Figure 2-1. Memory Map (Sheet MC68HC908AZ32A Data Sheet, Rev ...

Page 30

... EEPROM DIVIDER LOW REGISTER (EEDIVL) EEPROM NON-VOLATILE REGISTER (EENVR) EEPROM CONTROL REGISTER (EECR) RESERVED EEPROM ARRAY CONFIGURATION REGISTER (EEACR) MONITOR ROM (320 BYTES) UNIMPLEMENTED (32 BYTES) FLASH BLOCK PROTECT REGISTER (FLBPR) Figure 2-1. Memory Map (Sheet MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 31

... Data Direction Register A $0004 (DDRA) Data Direction Register B $0005 (DDRB) Figure 2-2. I/O Data, Status and Control Registers (Sheet Freescale Semiconductor RESERVED (7 BYTES) FLASH CONTROL REGISTER (FLCR) RESERVED (7 BYTES) UNIMPLEMENTED (48 BYTES) RESERVED (12 BYTES) VECTORS (52 BYTES) See Table 2-1 Figure 2-1. Memory Map (Sheet Figure 2-2, contain the I/O Data, Status and Control Registers ...

Page 32

... DDRG2 DDRG1 DDRH1 CPOL CPHA SPWOM SPE MODF SPTE MODFEN SPR1 WAKE ILTY PEN ILIE TE RE RWU R ORIE NEIE FEIE = Reserved R Freescale Semiconductor Bit 0 DDRC0 DDRD0 PTE0 PTF0 PTG0 PTH0 DDRE0 DDRF0 DDRG0 DDRH0 SPTIE SPR0 R0 T0 PTY SBK PEIE ...

Page 33

... Timer A Counter Register $0022 High (TACNTH) Timer A Counter Register $0023 Low (TACNTL) Timer A Modulo Register $0024 High (TAMODH) Timer A Modulo Register $0025 Low (TAMODL) Figure 2-2. I/O Data, Status and Control Registers (Sheet Freescale Semiconductor Bit Read: SCTE TC SCRF Write: Read ...

Page 34

... MS1A ELS1B ELS1A TOV1 MS2A ELS2B ELS2A TOV2 MS3A ELS3B ELS3A TOV3 MS4A ELS4B ELS4A TOV4 MS5A ELS5B ELS5A TOV5 = Reserved R Freescale Semiconductor Bit 0 CH0MAX Bit 8 Bit 0 CH1MAX Bit 8 Bit 0 CH2MAX Bit 8 Bit 0 CH3MAX Bit 8 Bit 0 CH4MAX Bit 8 Bit 0 CH5MAX ...

Page 35

... Timer B CH0 Register Low $0047 (TBCH0L) Timer B CH1 Status and Control Register (TBSC1) $0048 Timer B CH1 Register High $0049 (TBCH1H) Timer B CH1 Register Low $004A (TBCH1L) Figure 2-2. I/O Data, Status and Control Registers (Sheet Freescale Semiconductor Bit Read: Bit Write: Read: Bit ...

Page 36

... Read: EEDIV CLK Write: Read: Bit Write: Read: Bit Write: Read: 0 BRKE BRKA Write: = Unimplemented MC68HC908AZ32A Data Sheet, Rev PPS2 PPS1 PRST Reserved ILOP ILAD 0 LVI AZ32A EEMON SEC Reserved R Freescale Semiconductor Bit 0 PPS0 Bit 8 Bit 0 Bit 8 Bit 0 Bit Bit 8 Bit 0 0 ...

Page 37

... EEPROM Array Configuration $FE1F Register (EEACR) FLASH Block Protect Register $FF80 (FLBPR) FLASH Control Register $FF88 (FLCR) COP Control Register $FFFF (COPCTL) Figure 2-3. Additional Status and Control Registers (Continued) Freescale Semiconductor Bit Read: LVIOUT 0 0 Write: Read: EEDIVS Write: ...

Page 38

... SPI Transmit Vector (Low) $FFE4 SPI Receive Vector (High) $FFE5 SPI Receive Vector (Low) $FFE6 TIMB Overflow Vector (High) $FFE7 TIMB Overflow Vector (Low) $FFE8 TIMB CH1 Vector (High) $FFE9 TIMB CH1 Vector (Low) MC68HC908AZ32A Data Sheet, Rev. 2 — Continued on next page Freescale Semiconductor ...

Page 39

... Table 2-1. Vector Addresses (Continued) Highest Priority Freescale Semiconductor Address Vector Description $FFEA TIMB CH0 Vector (High) $FFEB TIMB CH0 Vector (Low) $FFEC TIMA Overflow Vector (High) $FFED TIMA Overflow Vector (Low) $FFEE TIMA CH3 Vector (High) $FFEF TIMA CH3 Vector (Low) ...

Page 40

... Memory Map 40 MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 41

... During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. Be careful when using nested subroutines. The CPU could overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Freescale Semiconductor NOTE NOTE NOTE MC68HC908AZ32A Data Sheet, Rev ...

Page 42

... RAM 42 MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 43

... Programming tools are available from Freescale. Contact your local Freescale representative for more information. A security feature prevents viewing of the FLASH contents security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor for details) NOTE MC68HC908AZ32A Data Sheet, Rev. 2 (1) ...

Page 44

... This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal set the same time Program operation selected 0 = Program operation unselected HVEN MC68HC908AZ32A Data Sheet, Rev Bit 0 MASS ERASE PGM Freescale Semiconductor ...

Page 45

... FLASH is protected from this start address to the end of FLASH memory at $FFFF. With this mechanism, the protect start address can be $XX00 and $XX80 (128 byte page boundaries) within the FLASH array. Start address of FLASH block protect Figure 4-3. FLASH Block Protect Start Address FLASH Protected Ranges: FLBPR[7:0] Freescale Semiconductor BPR6 BPR5 ...

Page 46

... FLBPR is not protected with special hardware or software; therefore, if this page is not protected by FLBPR and the vector locations are erased by either a page or a mass erase operation, FLBPR will also get erased. 46 NOTE NOTE MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 47

... Clear the HVEN bit. 10. Wait for a time after which the memory can be accessed in normal read mode. RCV A. Programming and erasing of FLASH locations can not be performed by code being executed from the same FLASH array. Freescale Semiconductor NOTE . NOTE NOTE MC68HC908AZ32A Data Sheet, Rev. 2 ...

Page 48

... Care must be taken however to ensure that these operations do not access any address within the FLASH array memory space such as the COP Control Register (COPCTL) at $FFFF. 48 NOTE Figure NOTE MC68HC908AZ32A Data Sheet, Rev. 2 4-4. Freescale Semiconductor ...

Page 49

... FLASH. Stop mode will suspend any FLASH program/erase operations and leave the memory in a Standby Mode. Standby Mode is the power saving mode of the FLASH module, in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is minimum. Freescale Semiconductor maximum or t maximum. t PROG HV ...

Page 50

... Wait for a time, t pgs 7 Write data to the FLASH address to be programmed 8 Wait for a time, t PROG Completed programming this row MC68HC908AZ32A Data Sheet, Rev Clear PGM bit Wait for a time, t nvh Clear HVEN bit Wait for a time, t rcv End of programming Freescale Semiconductor ...

Page 51

... EENVR and EEDIVNVR are nonvolatile EEPROM registers. They are programmed and erased in the same way as EEPROM bytes. The contents of these registers are loaded into their respective volatile registers during a MCU reset. The values in these read/write volatile registers define the EEPROM configurations. Freescale Semiconductor Figure 5-1. MC68HC908AZ32A Data Sheet, Rev. 2 ...

Page 52

... EEPROM Timebase MC68HC908AZ32A Data Sheet, Rev EEDIV10 EEDIV9 EEDIV3 EEDIV2 EEDIV1 0 0 EEDIV10 EEDIV9 EEDIV3 EEDIV2 EEDIV1 EEBP3 EEBP2 EEBP1 EERAS0 EELAT AUTO EEBP3 EEBP2 EEBP1 R = Reserved UNUSED Requirements). Freescale Semiconductor Bit 0 EEDIV8 EEDIV0 EEDIV8 EEDIV0 EEBP0 EEPGM 0 EEBP0 = Unused ...

Page 53

... EEDIVSECD bit in the EEDIVH is always loaded with 0 thereafter. Once this security feature is armed, erase and program mode are disabled for EEDIVHNVR and EEDIVLNVR. Modifications to the EEDIVH and EEDIVL registers are also disabled. Therefore, be cautious on programming a value into the EEDIVHNVR. Freescale Semiconductor and 5.5.2 EEPROM Array Configuration NOTE Address Range EEBP0 $0800– ...

Page 54

... EEPGM bit. Please see 5.5.1 EEPROM Control Register 54 Description 5.4.5 EEPROM Programming and Erasing for more information. MC68HC908AZ32A Data Sheet, Rev. 2 Table 5-2. Program Data Result in Binary in Binary n/a 1111:1111 1111:1110 1111:1110 1111:1101 1111:1100 1111:1011 1111:1000 1111:0111 1111:0000 Freescale Semiconductor and ...

Page 55

... For forward compatibility, software should not make any dependency on this delay time. E. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM array. Freescale Semiconductor (A) NOTE (B) (D) NOTE MC68HC908AZ32A Data Sheet, Rev ...

Page 56

... EEPGM. This is to allow time for removal of high voltage from the EEPROM array. 56 NOTE (B) for byte erase; t for block erase; t EEBLOCK NOTE /t . However, on other MCUs, this delay time EEBULK MC68HC908AZ32A Data Sheet, Rev. 2 (A) (B) (B) for bulk erase. EEBULK. (D) Freescale Semiconductor ...

Page 57

... EELAT — EEPROM Latch Control This read/write bit latches the address and data buses for programming the EEPROM array. EELAT cannot be cleared if EEPGM is still set. Reset clears this bit Buses configured for EEPROM programming or erase operation 0 = Buses configured for normal operation Freescale Semiconductor ...

Page 58

... These bits prevent blocks of EEPROM array from being programmed or erased EEPROM array block is protected 0 = EEPROM array block is unprotected See Table 5-4. 58 Programming, NOTE UNUSED UNUSED EEPRTCT EEBP3 Contents of EENVR ($FE1C) MC68HC908AZ32A Data Sheet, Rev. 2 5.4.5.3 EEPROM Erasing and 25.1. Bit 0 EEBP2 EEBP1 EEBP0 5.4.3 EEPROM Freescale Semiconductor ...

Page 59

... Write: Reset Programmed value the erased state. Figure 5-4. EEPROM Nonvolatile Register (EENVR) The EENVR will leave the factory programmed with $F0 such that the full array is available and unprotected. Freescale Semiconductor Address Range EEBP0 $0800–$087F EEBP1 $0880–$08FF EEBP2 $0900– ...

Page 60

... Programming/erasing the EEPROM with an improper EEDIV value may result in data lost and reduce endurance of the EEPROM device Contents of EEDIVHNVR ($FE10), Bits [6: EEDIV6 EEDIV5 EEDIV4 EEDIV3 Contents of EEDIVLNVR ($FE11) -6 +0.5] NOTE MC68HC908AZ32A Data Sheet, Rev Bit 0 EEDIV10 EEDIV9 EEDIV8 2 1 Bit 0 EEDIV2 EEDIV1 EEDIV0 Freescale Semiconductor ...

Page 61

... Low-Power Modes The WAIT and STOP instructions can put the MCU in low power-consumption standby modes. 5.6.1 Wait Mode The WAIT instruction does not affect the EEPROM possible to start the program or erase sequence on the EEPROM and put the MCU in wait mode. Freescale Semiconductor ...

Page 62

... EEPROM is only possible after the programming sequence has completed. If stop mode is entered while EELAT and EEPGM is cleared, the programming sequence will be terminated abruptly. In either case, the data integrity of the EEPROM is not guaranteed. 62 MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 63

... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 6.3 CPU Registers Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map. Freescale Semiconductor MC68HC908AZ32A Data Sheet, Rev ...

Page 64

... CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 6-1. CPU Registers Unaffected by reset Figure 6-2. Accumulator ( Figure 6-3. Index Register (H:X) MC68HC908AZ32A Data Sheet, Rev Bit 0 Bit Freescale Semiconductor ...

Page 65

... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: Freescale Semiconductor ...

Page 66

... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result NOTE MC68HC908AZ32A Data Sheet, Rev Bit Freescale Semiconductor ...

Page 67

... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. Freescale Semiconductor MC68HC908AZ32A Data Sheet, Rev. 2 Arithmetic/Logic Unit (ALU) ...

Page 68

... REL 27 rr – – – – – – REL – – – – – – REL 28 rr – – – – – – REL 29 rr – – – – – – REL 22 rr Freescale Semiconductor ...

Page 69

... Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? IRQ = 1 PC ← (PC rel ? IRQ = 0 (A) & (M) ⊕ PC ← (PC rel ? ( – – – – – – REL PC ← ...

Page 70

... INH 4A INH 5A – – – IX1 SP1 9E6A ff – – – – INH 52 IMM A8 ii DIR B8 dd EXT IX2 – – – IX1 SP1 9EE8 ff SP2 9ED8 ee ff DIR 3C dd INH 4C INH 5C – – – IX1 SP1 9E6C ff Freescale Semiconductor ...

Page 71

... ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack Freescale Semiconductor Description PC ← Jump Address PC ← (PC Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – ← Unconditional Address A ← (M) H:X ← (M ← (M) ...

Page 72

... DIR 35 dd – – 0 – – – INH 8E DIR BF dd EXT IX2 – – – IX1 SP1 9EEF ff SP2 9EDF ee ff IMM A0 ii DIR B0 dd EXT IX2 – – IX1 SP1 9EE0 ff SP2 9ED0 ee ff Freescale Semiconductor ...

Page 73

... M Memory location N Negative bit 6.8 Opcode Map See Table 6-2. Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...

Page 74

Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...

Page 75

... CPU enable/disable timing Register Name SIM Break Status Register (SBSR) SIM Reset Status Register (SRSR) SIM Break Flag Control Register (SBFCR) Table 7-1. I/O Register Address Summary Register Address Freescale Semiconductor Figure 7-2. Figure 7 summary of the SIM input/output (I/O) Bit ...

Page 76

... CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO CGM) COP CLOCK CGMXCLK (FROM CGM) CGMOUT (FROM CGM) INTERNAL CLOCKS LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE Freescale Semiconductor ...

Page 77

... CGMXCLK cycles. See In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Freescale Semiconductor Chapter 8 Clock Generator Module CGMXCLK ...

Page 78

... Counter), but an external reset does not. Each of Table 7-3 for details. Table 7-3. PIN Bit Set Timing Number of Cycles Required to Set PIN 4163 (4096 + ( VECT H Figure 7-4. External Reset Timing MC68HC908AZ32A Data Sheet, Rev. 2 7.7 SIM Registers). Figure 7-4 shows the relative VECT L Freescale Semiconductor ...

Page 79

... The RST pin is driven low during the oscillator stabilization time. • The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. Freescale Semiconductor 7-5. RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES Figure 7-5. Internal Reset Timing ...

Page 80

... ROM memory map device and may as a result generate unwanted resets CYCLES CYCLES Figure 7-7. POR Recovery NOTE MC68HC908AZ32A Data Sheet, Rev. 2 $FFFE $FFFF Chapter 13 Computer Freescale Semiconductor ...

Page 81

... Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) • Reset • Break interrupts Freescale Semiconductor rises above V DD LVIR 7.6.2 Stop Mode 7.3.2 Active Resets from Internal Sources MC68HC908AZ32A Data Sheet, Rev. 2 SIM Counter voltage falls to the V DD ...

Page 82

... SP – – – – – 1[15: Figure 7-8 Interrupt Entry SP – – – – 1 [7:0] PC – 1 [15:8] Figure 7-9. Interrupt Recovery MC68HC908AZ32A Data Sheet, Rev. 2 Figure 7-8 shows VECT H VECT L START ADDR CCR V DATA H V DATA L OPCODE OPCODE OPERAND Freescale Semiconductor ...

Page 83

... YES (AS MANY INTERRUPTS AS EXIST ON CHIP) Freescale Semiconductor FROM RESET YES BREAK INTERRUPT? I BIT SET BIT SET? NO YES IRQ1 INTERRUPT? NO STACK CPU REGISTERS. LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. SWI YES INSTRUCTION? NO YES RTI UNSTACK CPU REGISTERS. INSTRUCTION? NO EXECUTE INSTRUCTION. Figure 7-10. Interrupt Processing MC68HC908AZ32A Data Sheet, Rev ...

Page 84

... A software interrupt pushes PC onto the stack. A software interrupt does not push PC – hardware interrupt does. 84 NOTE CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Interrupt Recognition Example NOTE MC68HC908AZ32A Data Sheet, Rev. 2 BACKGROUND ROUTINE Freescale Semiconductor ...

Page 85

... BW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the configuration register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. Freescale Semiconductor Module. The SIM puts the CPU into the break state by MC68HC908AZ32A Data Sheet, Rev. 2 ...

Page 86

... WAIT ADDR + 1 SAME NEXT OPCODE Figure 7-12. Wait Mode Entry Timing $6E0C $00FF $00FE $A6 $01 $0B $6E RST pin OR CPU interrupt OR break interrupt 32 32 Cycles Cycles $A6 NOTE MC68HC908AZ32A Data Sheet, Rev. 2 SAME SAME SAME $00FD $00FC RST VCT H RST VCT L Freescale Semiconductor ...

Page 87

... This status bit is useful in applications requiring a return to wait mode after exiting from a break interrupt. Clear BW by writing it. Reset clears BW Wait mode was exited by break interrupt 0 = Wait mode was not exited by break interrupt Freescale Semiconductor Figure 7-15 STOP ADDR + 1 PREVIOUS DATA NEXT OPCODE ...

Page 88

... Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset was caused by the LVI circuit 0 = POR or read of SRSR PIN COP ILOP ILAD Unimplemented MC68HC908AZ32A Data Sheet, Rev Bit 0 0 LVI Freescale Semiconductor ...

Page 89

... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Freescale Semiconductor ...

Page 90

... System Integration Module (SIM) 90 MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 91

... OSC2 pin is the output. The SIMOSCEN signal enables the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock. Freescale Semiconductor MC68HC908AZ32A Data Sheet, Rev ...

Page 92

... LOOP CONTROLLED FILTER OSCILLATOR PLL ANALOG BANDWIDTH INTERRUPT CONTROL CONTROL AUTO ACQ PLLIE PLLF MUL7–MUL4 CGMVCLK FREQUENCY DIVIDER Figure 8-1. CGM Block Diagram MC68HC908AZ32A Data Sheet, Rev. 2 CGMXCLK A CGMOUT ÷ *When CGMOUT = B PTC3 MONITOR MODE USER MODE CGMINT Freescale Semiconductor ...

Page 93

... VCO feedback clock, CGMVDV, running at a frequency f Programming the PLL for more information. The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The Freescale Semiconductor Bit ...

Page 94

... Circuit. The PLL is automatically in Register read-only indicator of the mode of the Modes. . See Chapter 25 Electrical unt . See unl Register. MC68HC908AZ32A Data Sheet, Rev. 2 Register. 8.5.2 PLL 8.3.3 Base Clock Selector , and is cleared when trk Specifications. , and is cleared Lock Chapter 25 Electrical Freescale Semiconductor ...

Page 95

... VCLKDES BUSDES = 4 × 8 MHz = 32 MHz Example: f VCLKDES 3. Using a reference frequency, f multiplier, N. Round the result to the nearest integer. Freescale Semiconductor , after entering tracking mode before selecting the PLL as the al Table 8-2. Variable Definitions Definition Desired Bus Clock Frequency Desired VCO Clock Frequency ...

Page 96

... CGMVCLK ----------------------- - L = round ⎝ ⎠ f NOM 32 MHz L ------------------------------- - Example: = 4.9152 MHz . The center-of-range frequency is the CGMVRS NOTE f NOM ≤ – --------------- - CGMVCLK CGMVRS 8.3.2.4 Programming the Circuit. MC68HC908AZ32A Data Sheet, Rev BUSDES BUSDES = PLL, does not account for two possible Freescale Semiconductor or ...

Page 97

... Feedback resistor • Series resistor, R (optional) S SIMOSCEN can be 0 (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data. S Freescale Semiconductor CGMXCLK * Figure 8-3. CGM External Connections MC68HC908AZ32A Data Sheet, Rev. 2 Functional Description Figure 8- BYP 97 ...

Page 98

... Also, the frequency and amplitude of CGMXCLK can be unstable at startup. 98 NOTE should be placed as close to the CGMXFC F connection DDA NOTE Figure 8-3 shows only the logical relation of CGMXCLK MC68HC908AZ32A Data Sheet, Rev. 2 8.9 Acquisition/Lock pin to the same voltage DDA ) and CGMXCLK Freescale Semiconductor ...

Page 99

... Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit Change in lock condition change in lock condition Do not inadvertently clear the PLLF bit. Be aware that any read or read-modify-write operation on the PLL control register clears the PLLF bit. Freescale Semiconductor PLLF ...

Page 100

... ACQ bit before turning on the PLL. Reset clears the AUTO bit Automatic bandwidth control 0 = Manual bandwidth control 100 NOTE Circuit LOCK 0 ACQ XLD Unimplemented MC68HC908AZ32A Data Sheet, Rev. 2 8.3.3 Base Clock Selector 8.3.3 Base Clock 2 1 Bit Freescale Semiconductor ...

Page 101

... The PLL programming register contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the VCO. Address: $001E Bit 7 Read: MUL7 Write: Reset: 0 Figure 8-6. PLL Programming Register (PPG) Freescale Semiconductor MUL6 MUL5 MUL4 VRS7 1 1 ...

Page 102

... VCO Frequency Multiplier (N) 0000 0001 0010 0011 1101 1110 1111 . (See 8.3.2.1 Circuits, VRS Exceptions. A value the VCO range for more information.) Reset initializes the bits NOTE MC68HC908AZ32A Data Sheet, Rev 8.3.2.4 Programming the PLL, and 8.3.3 Base Clock Selector Circuit Freescale Semiconductor ...

Page 103

... To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. Freescale Semiconductor NOTE Module. ...

Page 104

... Manual and Automatic PLL Bandwidth , of not more than ±100%. In automatic – f )/f des orig des 8.3.2.3 Manual and Automatic PLL Bandwidth MC68HC908AZ32A Data Sheet, Rev not more than ±100%. In )/f orig des Modes), . Lock time is Lock Modes). Freescale Semiconductor . trk ...

Page 105

... Choosing the lower size may seem attractive for acquisition time improvement, but the PLL may become unstable. Also, always choose a capacitor with a tight tolerance (±20% or better) and low dissipation. Freescale Semiconductor 8-1). This frequency is the input to the phase detector and controls how ...

Page 106

... F MC68HC908AZ32A Data Sheet, Rev. 2 Capacitor). is the K factor when the PLL acq ⎞ ⎠ ⎞ ⎠ Modes). A certain number required to ascertain that the TRK , is an integer ACQ /f TRK CGMRDV before selecting the PLL Lock 8.9.2 Parametric Freescale Semiconductor , TRK . ...

Page 107

... The resultant waveform can be captured on an oscilloscope and used to determine the typical lock time for the microcontroller and the associated external application circuit. e.g. Init. low The filter capacitor should be fully discharged prior to making any measurements. Freescale Semiconductor t LOCK t ACQ t ...

Page 108

... Clock Generator Module (CGM) 108 MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 109

... LVI disabled during stop mode To have the LVI enabled in stop mode, the LVIPWR must logic 1 and the LVISTOP bit must logic 1. Take note that by enabling the LVI in stop mode, the stop I Freescale Semiconductor NOTE , and remains at or below that level for at TRIPF ...

Page 110

... AZ and AB families doubt, check with your local field applications representative. 110 Chapter 14 Low Voltage Inhibit Chapter 14 Low Voltage Inhibit 7.6.2 Stop Mode). NOTE Chapter 13 Computer Operating Properly Chapter 13 Computer Operating Properly CAUTION MC68HC908AZ32A Data Sheet, Rev. 2 (LVI)). (LVI)). (COP). Freescale Semiconductor ...

Page 111

... EEPROM read protection in monitor mode enabled 0 = EEPROM read protection in monitor mode disabled AZ32A — Device indicator This read-only bit is used to indicate that the MC68HC908AZ32A is an ‘A’ suffix version HC08 rather than a non-’A’ ‘A’ version 0 = Non-’A’ version Freescale Semiconductor AZ32A EEMON- ...

Page 112

... Configuration Register (CONFIG-2) 112 MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 113

... CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. structure of the break module. IAB[15:0] Figure 11-1. Break Module Block Diagram Freescale Semiconductor IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR CONTROL ...

Page 114

... The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 114 Bit Bit Bit BRKE BRKA Unimplemented Figure 11-2. I/O Register Summary Register BRKH BRKL Address $FE0C $FE0D is present on the RST pin. Hi MC68HC908AZ32A Data Sheet, Rev BSCR $FE0B Freescale Semiconductor Bit 0 Bit 8 0 Bit ...

Page 115

... This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic before exiting the break routine. Reset clears the BRKA bit (When read) Break address match 0 = (When read) No break address match Freescale Semiconductor 7.7.1 SIM Break Status ...

Page 116

... The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Register: BRKH Address: $FE0C Bit 7 Read: Bit 15 Write: Reset: 0 Read: Bit 7 Write: Reset: 0 Figure 11-4. Break Address Registers (BRKH and BRKL) 116 BRKL $FE0D MC68HC908AZ32A Data Sheet, Rev Bit Bit Bit Freescale Semiconductor ...

Page 117

... All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. Freescale Semiconductor Security). MC68HC908AZ32A Data Sheet, Rev. 2 ...

Page 118

... MC68HC908AZ32A Data Sheet, Rev 68HC08 10 kΩ RST 0.1 μ KΩ IRQ 9.1V CGMXFC 0.022 μF OSC1 * X1 10 MΩ OSC2 V DDA V /V DDA DDAREF 0.1 μF V SSA V SS 0.1 μ kΩ PTA0 PTC3 kΩ 10 kΩ PTC0 A (SEE PTC1 B NOTE.) Freescale Semiconductor ...

Page 119

... IRQ and/or RESET pin while in monitor mode, the SIM as- HI serts its COP enable output. The COP is enabled or disabled by the COPD bit in the configuration reg- ister. (see 25.1.4 5.0 Volt DC Electrical Freescale Semiconductor Table 12-1. Mode Selection PTA0 PTC3 Mode ...

Page 120

... Figure 12-5. Break Transaction MC68HC908AZ32A Data Sheet, Rev. 2 NEXT START STOP BIT 6 BIT 7 BIT BIT NEXT START STOP BIT BIT 6 BIT 7 BIT STOP NEXT BIT 6 BIT 7 BIT START BIT ADDR. LOW ADDR. LOW DATA RESULT 12-5). When the monitor receives a break Freescale Semiconductor ...

Page 121

... Specifies 2-byte address in high byte:low byte order; low byte followed by data byte Data Returned None Opcode $49 Command Sequence SENT TO MONITOR WRITE WRITE ECHO Freescale Semiconductor READ ADDR. HIGH ADDR. HIGH ADDR. HIGH ADDR. HIGH ADDR. LOW MC68HC908AZ32A Data Sheet, Rev. 2 Functional Description ADDR. LOW ADDR. LOW ...

Page 122

... Reads stack pointer Operand None Data Returned Returns stack pointer in high byte:low byte order Opcode $0C Command Sequence SENT TO MONITOR ECHO 122 IREAD IREAD DATA IWRITE IWRITE ECHO READSP READSP SP HIGH MC68HC908AZ32A Data Sheet, Rev. 2 DATA RESULT DATA DATA SP LOW RESULT Freescale Semiconductor ...

Page 123

... Care should be taken when setting the baud rate since incorrect baud rate setting can result in communications failure. Freescale Semiconductor SENT TO MONITOR RUN RUN ECHO Baud rate Closest PC baud PC PTC3=1 PTC3=0 PTC3=1 28.98 57 ...

Page 124

... After receiving the eight security bytes from the host, the MCU transmits a break character signalling that it is ready to receive a command. The MCU does not transmit a break character until after the host sends the eight security bytes. 124 NOTE 24 BUS CYCLES (MINIMUM Figure 12-6. Monitor Mode Entry Timing NOTE MC68HC908AZ32A Data Sheet, Rev Freescale Semiconductor ...

Page 125

... Hi Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly. Freescale Semiconductor NOTE NOTE MC68HC908AZ32A Data Sheet, Rev During the break ...

Page 126

... The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up. 126 Figure 13-1. 12-BIT COP PRESCALER 6-BIT COP COUNTER CLEAR COP COUNTER Figure 13-1. COP Block Diagram 13.4 COP Control MC68HC908AZ32A Data Sheet, Rev. 2 RESET RESET STATUS REGISTER Register), clears the COP Freescale Semiconductor ...

Page 127

... Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 13.7.1 Wait Mode The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. Freescale Semiconductor (CONFIG-1)). (CONFIG-1)). 6 5 ...

Page 128

... The STOP bit in the configuration register (CONFIG-1) enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit. 13.8 COP Module During Break Interrupts The COP is disabled during a break interrupt when V 128 is present on the RST pin. Hi MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 129

... TRIPR Operation). The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR). An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices. Freescale Semiconductor voltage falls to the LVI trip voltage. DD NOTE Chapter 9 Configuration Register ...

Page 130

... TRIPF for only one CPU cycle to bring the MCU out of reset. TRIPR MC68HC908AZ32A Data Sheet, Rev. 2 FROM CONFIG-1 LVIRST LVI RESET level, software can monitor V level, enabling LVI resets allows the LVI level for nine or more consecutive TRIPF Freescale Semiconductor Bit ...

Page 131

... With the LVIPWR bit in the configuration register programmed to logic 1, the LVI module is active after a WAIT instruction. With the LVIRST bit in the configuration register programmed to logic 1, the LVI module can generate a reset and bring the MCU out of wait mode. Freescale Semiconductor voltages below the LVI TRIPF 6 ...

Page 132

... Note that the LVI feature is intended to provide the safe shutdown of the microcontroller and thus protection of related circuitry prior to any application not intended that users operate the microcontroller at lower than specified operating voltage V 132 voltage collapsing completely to an unsafe level. DD MC68HC908AZ32A Data Sheet, Rev Freescale Semiconductor ...

Page 133

... When an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both of the following occur: • Vector fetch or software clear • Return of the interrupt pin to logic 1 Freescale Semiconductor MC68HC908AZ32A Data Sheet, Rev. 2 Figure 15-1 shows the 133 ...

Page 134

... Figure 15-1. IRQ Block Diagram Bit Read Write Reserved Figure 15-2. IRQ I/O Register Summary NOTE MC68HC908AZ32A Data Sheet, Rev CPU FOR BIL/BIH INSTRUCTIONS IRQF SYNCHRO- IRQ NIZER INTERRUPT REQUEST HIGH TO MODE VOLTAGE SELECT DETECT LOGIC IRQF 0 IMASK R R ACK Freescale Semiconductor Bit 0 MODE ...

Page 135

... YES Freescale Semiconductor FROM RESET I BIT SET? NO YES INTERRUPT? NO STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS. INSTRUCTION? NO EXECUTE INSTRUCTION. Figure 15-3. IRQ Interrupt Flowchart MC68HC908AZ32A Data Sheet, Rev. 2 ...

Page 136

... To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch. 136 NOTE 7.7.3 SIM Break Flag Control Register MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 137

... IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE IRQ1 interrupt requests on falling edges and low levels 0 = IRQ1 interrupt requests on falling edges only Freescale Semiconductor ...

Page 138

... External Interrupt Module (IRQ1) 138 MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 139

... SCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an SCI input or output reflects the name of the shared port pin. SCI I/O pins.The generic pin names appear in the text of this section. Freescale Semiconductor Table 16-1 shows the full names and the generic names of the MC68HC908AZ32A Data Sheet, Rev ...

Page 140

... SCALER GENERATOR DATA SELECTION ÷ 16 CONTROL Figure 16-1. SCI Module Block Diagram MC68HC908AZ32A Data Sheet, Rev. 2 TxD PTE0/SCTxD SCI DATA REGISTER TRANSMIT TxD SHIFT REGISTER TXINV R8 T8 ORIE NEIE FEIE PEIE LOOPS ENSCI TRANSMIT CONTROL M WAKE ILTY PEN PTY Freescale Semiconductor ...

Page 141

... SCI Status Register 2 (SCS2) Write: Reset: Read: SCI Data Register (SCDR) Write: Reset: Read: SCI Baud Rate Register (SCBR) Write: Reset: Table 16-2. SCI I/O Register Address Summary Register SCC1 Address $0013 Freescale Semiconductor Bit LOOPS ENSCI TXINV SCTIE TCIE SCRIE ...

Page 142

... GENERATION T8 SCTE SCTE SCTIE SCTIE TC TC TCIE TCIE Figure 16-4. SCI Transmitter MC68HC908AZ32A Data Sheet, Rev. 2 Figure 16-3. NEXT START STOP BIT BIT PARITY OR DATA NEXT BIT START BIT 8 STOP BIT BIT TxD TRANSMITTER CONTROL LOGIC SBK LOOPS ENSCI TE Freescale Semiconductor ...

Page 143

... Read: SCI Data Register (SCDR) Write: Reset: Read: SCI Baud Rate Register (SCBR) Write: Reset: Figure 16-5. SCI Transmitter I/O Register Summary Table 16-3. SCI Transmitter I/O Address Summary Register SCC1 Address $0013 Freescale Semiconductor Bit LOOPS ENSCI TXINV SCTIE TCIE ...

Page 144

... Clears the SCI data register (SCDR) • Clears the R8 bit in SCC3 • Sets the break flag bit (BKF) in SCS2 • May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits 144 MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 145

... SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. 16.4.3 Receiver Figure 16-6 shows the structure of the SCI receiver. Freescale Semiconductor NOTE NOTE MC68HC908AZ32A Data Sheet, Rev. 2 Functional Description 145 ...

Page 146

... BAUD ÷ 16 DIVIDER DATA H RECOVERY ALL ZEROS WAKEUP LOGIC PARITY CHECKING IDLE ILIE SCRF SCRIE OR ORIE NF NEIE FE FEIE PE PEIE MC68HC908AZ32A Data Sheet, Rev. 2 SCI DATA REGISTER 11-BIT RECEIVE SHIFT REGISTER RWU SCRF IDLE R8 ILIE SCRIE OR ORIE NF NEIE FE FEIE PE PEIE Freescale Semiconductor ...

Page 147

... Read: SCI Data Register (SCDR) Write: Reset: Read: SCI Baud Rate Register (SCBR) Write: Reset: Figure 16-7. SCI I/O Receiver Register Summary Table 16-4. SCI Receiver I/O Address Summary Register SCC1 Address $0013 Freescale Semiconductor Bit LOOPS ENSCI TXINV SCTIE TCIE ...

Page 148

... When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. RxD SAMPLES RT CLOCK RT CLOCK STATE RT CLOCK RESET 148 START BIT START BIT START BIT DATA QUALIFICATION VERIFICATION SAMPLING Figure 16-8. Receiver Data Sampling MC68HC908AZ32A Data Sheet, Rev. 2 LSB Freescale Semiconductor ...

Page 149

... RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. Freescale Semiconductor Table 16-5. Start Bit Verification Start Bit Verification ...

Page 150

... The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. RECEIVER RT CLOCK 150 Table 16-7. Stop Bit Recovery Framing Error Flag MSB DATA SAMPLES Figure 16-9. Slow Data MC68HC908AZ32A Data Sheet, Rev. 2 Table 16-7 Noise Flag STOP Freescale Semiconductor ...

Page 151

... RT cycles = 176 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is Freescale Semiconductor Figure 16-9, the receiver counts 154 RT cycles at the point 154 147 – ...

Page 152

... Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU interrupt requests. 152 NOTE MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 153

... The PTE0/SCTxD pin is the serial data output from the SCI transmitter. The SCI shares the PTE0/SCTxD pin with port E. When the SCI is enabled, the PTE0/SCTxD pin is an output regardless of the state of the DDRE2 bit in data direction register E (DDRE). Freescale Semiconductor Module). MC68HC908AZ32A Data Sheet, Rev. 2 ...

Page 154

... SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit Loop mode enabled 0 = Normal operation enabled 154 ENSCI TXINV M WAKE MC68HC908AZ32A Data Sheet, Rev Bit 0 ILLTY PEN PTY Freescale Semiconductor ...

Page 155

... Table 16-8). Reset clears the PTY bit Odd parity 0 = Even parity Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Freescale Semiconductor NOTE Table 16-8). When enabled, the parity function Table NOTE MC68HC908AZ32A Data Sheet, Rev. 2 ...

Page 156

... None 1 9 None 1 7 Even 1 7 Odd 1 8 Even 1 8 Odd TCIE SCRIE ILIE MC68HC908AZ32A Data Sheet, Rev. 2 Stop Character Bits Length 1 10 Bits 1 11 Bits 1 10 Bits 1 10 Bits 1 11 Bits 1 11 Bits 2 1 Bit 0 RE RWU SBK Freescale Semiconductor ...

Page 157

... Transmit break characters break characters being transmitted Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble. Freescale Semiconductor NOTE NOTE NOTE MC68HC908AZ32A Data Sheet, Rev. 2 ...

Page 158

... This read/write bit enables SCI receiver CPU interrupt requests generated by the parity error bit, PE. Reset clears PEIE SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled 158 ORIE Unimplemented R = Reserved MC68HC908AZ32A Data Sheet, Rev Bit 0 NEIE FEIE PEIE Unaffected Freescale Semiconductor ...

Page 159

... This clearable, read-only bit is set when consecutive logic 1s appear on the receiver input. IDLE generates an SCI error CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must Freescale Semiconductor 6 5 ...

Page 160

... READ SCDR BYTE 1 BYTE 2 DELAYED FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1 SCRF = READ SCDR BYTE 1 Figure 16-15. Flag Clearing Sequence MC68HC908AZ32A Data Sheet, Rev. 2 BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 Freescale Semiconductor ...

Page 161

... RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character. Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress Reception in progress reception in progress Freescale Semiconductor ...

Page 162

... SCP0. SCP[1:0] 162 Unaffected by Reset Figure 16-17. SCI Data Register (SCDR) NOTE SCP1 SCP0 Unimplemented R = Reserved Table 16-9. SCI Baud Rate Prescaling Prescaler Divisor (PD MC68HC908AZ32A Data Sheet, Rev Bit Bit 0 SCR2 SCR1 SCR0 Table 16-9. Reset clears SCP1 Freescale Semiconductor ...

Page 163

... Baud rate where crystal frequency Crystal PD = prescaler divisor BD = baud rate divisor Table 16-11 shows the SCI baud rates that can be generated with a 4.9152-MHz crystal. Freescale Semiconductor Table 16-10. SCI Baud Rate Selection Baud Rate Divisor (BD) 000 001 010 011 100 16 101 ...

Page 164

... MC68HC908AZ32A Data Sheet, Rev. 2 Baud Rate (f = 4.9152 MHz) Crystal 76,800 38,400 19,200 9600 4800 2400 1200 600 25,600 12,800 6400 3200 1600 800 400 200 19,200 9600 4800 2400 1200 600 300 150 5908 2954 1477 739 369 185 92 46 Freescale Semiconductor ...

Page 165

... Table 17-1 shows the full names of the SPI I/O pins. The generic pin names appear in the text that follows. SPI Generic Pin Name Full SPI Pin Name Freescale Semiconductor Table 17-1. Pin Name Conventions MISO MOSI PTE5/MISO PTE6/MOSI MC68HC908AZ32A Data Sheet, Rev ...

Page 166

... SPRF OVRF ERRIE Reserved Figure 17-1. SPI I/O Register Summary MC68HC908AZ32A Data Sheet, Rev. 2 Address $0010 $0011 $0012 shows the structure of the SPI module CPOL CPHA SPWOM SPE MODF SPTE MODFEN SPR1 Unaffected by Reset = Unimplemented Freescale Semiconductor Bit 0 SPTIE 0 SPR0 ...

Page 167

... BUS CLOCK ÷ 2 ÷ 8 CLOCK DIVIDER ÷ 32 ÷ 128 CLOCK SPMSTR SPE SELECT SPR1 TRANSMITTER CPU INTERRUPT REQUEST RECEIVER/ERROR CPU INTERRUPT REQUEST Freescale Semiconductor INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER RECEIVE DATA REGISTER CLOCK LOGIC SPR0 SPMSTR CPHA MODFEN ERRIE ...

Page 168

... SPI data register before another byte enters the shift register. 168 NOTE 17.13.1 SPI Control Table Register). Through the SPSCK pin, the baud rate generator of the MISO MISO MOSI MOSI SPSCK SPSCK MC68HC908AZ32A Data Sheet, Rev. 2 Register. 17-3). SLAVE MCU SHIFT REGISTER SS Freescale Semiconductor 17.6.2 ...

Page 169

... In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. Before writing to the CPOL bit or the CPHA bit (SPCR), disable the SPI by clearing the SPI enable bit (SPE). Freescale Semiconductor 17.5 Transmission NOTE NOTE MC68HC908AZ32A Data Sheet, Rev ...

Page 170

... This format may be preferable in systems having only one master and only one slave driving the MISO data line. 170 BIT 6 BIT 5 BIT 4 BIT 3 BIT 6 BIT 5 BIT 4 BIT 3 MC68HC908AZ32A Data Sheet, Rev BIT 2 BIT 1 LSB BIT 2 BIT 1 LSB Freescale Semiconductor ...

Page 171

... SPI bit time. That is, the maximum delay between the write to SPDR and the start of the SPI transmission is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128. Freescale Semiconductor 2 3 ...

Page 172

... EARLIEST LATEST 2 POSSIBLE START POINTS SCK = INTERNAL CLOCK ÷ 8; EARLIEST 8 POSSIBLE START POINTS SCK = INTERNAL CLOCK ÷ 32; EARLIEST 32 POSSIBLE START POINTS SCK = INTERNAL CLOCK ÷ 128; EARLIEST 128 POSSIBLE START POINTS MC68HC908AZ32A Data Sheet, Rev. 2 BIT 6 BIT LATEST LATEST LATEST Freescale Semiconductor ...

Page 173

... BYTE 1 SETS SPRF BIT. 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. 3 CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. 4 BYTE 2 SETS SPRF BIT. Figure 17-7. Missed Read of Overflow Condition Freescale Semiconductor BYTE 2 BYTE CPU READS SPSCRW WITH SPRF BIT SET AND OVRF BIT CLEAR ...

Page 174

... CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 11 BYTE 4 SETS SPRF BIT. 12 CPU READS SPSCR. 13 CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT. 14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. Figure MC68HC908AZ32A Data Sheet, Rev. 2 BYTE 17-9 not possible to enable Freescale Semiconductor ...

Page 175

... Also, the slave SPI ignores all incoming SPSCK clocks, even if a transmission has begun. To clear the MODF flag, read the SPSCR and then write to the SPCR register. This entire clearing procedure must occur with no MODF condition existing or else the flag will not be cleared. Freescale Semiconductor NOTE NOTE 17.5 Transmission ...

Page 176

... SPI Transmitter CPU Interrupt Request (SPTIE = 1) SPI Receiver CPU Interrupt Request (SPRIE = 1) SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1) SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1, MODFEN = 1) SPTE SPTIE SPE SPRIE SPRF MC68HC908AZ32A Data Sheet, Rev. 2 SPI TRANSMITTER CPU INTERRUPT REQUEST SPI RECEIVER/ERROR CPU INTERRUPT REQUEST Freescale Semiconductor ...

Page 177

... For a slave, the transmit data buffer allows back-to-back transmissions to occur without the slave having to time the write of its data between the transmissions. Also new data is written to the data buffer, the last value contained in the shift register will be the next data word transmitted. Freescale Semiconductor 3 5 ...

Page 178

... The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR, $FE03) enables software to clear status bits during the break state. (See 178 17.7 7.7.3 SIM Break Flag Control MC68HC908AZ32A Data Sheet, Rev. 2 Interrupts). Register). Freescale Semiconductor ...

Page 179

... MOSI pin and receives data on its MISO pin. When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I/O port. Freescale Semiconductor 2 C) capability (requiring software support master in a ...

Page 180

... General-Purpose I/O; SS Ignored by SPI Slave Master without MODF General-Purpose I/O; SS Ignored by SPI Master with MODF MC68HC908AZ32A Data Sheet, Rev. 2 17-11. BYTE 3 17.13.2 SPI Status and Control 17.6.2 Mode Fault Error). For the state of State of SS Logic Input-Only to SPI Input-Only to SPI Freescale Semiconductor ...

Page 181

... CPOL — Clock Polarity Bit This read/write bit determines the logic state of the SPSCK pin between transmissions. (See 17-4 and Figure 17-5.) To transmit data between SPI modules, the SPI modules must have identical CPOL bits. Reset clears the CPOL bit. Freescale Semiconductor SPMSTR ...

Page 182

... Transmit data register empty The SPI status and control register also contains bits that perform these functions: • Enable error interrupts • Enable mode fault error detection • Select master SPI baud rate 182 MC68HC908AZ32A Data Sheet, Rev. 2 Figure 17.9 Freescale Semiconductor ...

Page 183

... This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. SPTE generates an SPTE CPU interrupt request if the SPTIE bit in the SPI control register is set also. Do not write to the SPI data register unless the SPTE bit is high. Freescale Semiconductor ...

Page 184

... CGMOUT = base clock output of the clock generator module (CGM), see Chapter 8 Clock Generator Module BD = baud rate divisor 184 Select)). Baud Rate Divisor (BD 128 CGMOUT Baud rate = ------------------------- - × (CGM). MC68HC908AZ32A Data Sheet, Rev. 2 17.6.2 Mode Table 17-5. SPR1 and Freescale Semiconductor ...

Page 185

... See Address: $0012 Bit 7 Read: R7 Write: T7 Reset: R7–R0/T7–T0 — Receive/Transmit Data Bits Do not use read-modify-write instructions on the SPI data register since the buffer read is not the same as the buffer written. Freescale Semiconductor Figure 17- ...

Page 186

... Serial Peirpheral Interface (SPI) 186 MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 187

... Frequency Internal Bus Clock Prescaler Selection – External TIMA Clock Input (4 MHz Maximum Frequency) • Free-Running or Modulo Up-Count Operation • Toggle Any Channel Pin on Overflow • TIMA Counter Stop and Reset Bits Freescale Semiconductor MC68HC908AZ32A Data Sheet, Rev. 2 Figure 18-1 is 187 ...

Page 188

... RUPT LOGIC CH1IE TOV2 PTF0 PTF0/TCH2 CH2MAX LOGIC INTER- RUPT LOGIC CH2IE TOV3 PTF1 PTF1/TCH3 CH3MAX LOGIC INTER- RUPT LOGIC CH3IE TOV4 PTF2 PTF2/TCH4/TACH4 CH5MAX LOGIC INTER- RUPT LOGIC CH4IE TOV5 PTF3 PTF3/TCH5/TACH5 CH5MAX LOGIC INTER- RUPT LOGIC CH5IE Freescale Semiconductor ...

Page 189

... The TIMA counter modulo registers, TAMODH–TAMODL, control the modulo value of the TIMA counter. Software can read the TIMA counter value at any time without affecting the counting sequence. The six TIMA channels are programmable independently as input capture or output compare channels. Freescale Semiconductor Bit ...

Page 190

... When the counter reaches the value in the registers of an output compare channel, the TIMA can set, clear or toggle the channel pin. Output compares can generate TIMA CPU interrupt requests. 190 18.8.5 TIMA Channel MC68HC908AZ32A Data Sheet, Rev. 2 Registers). Because Freescale Semiconductor ...

Page 191

... PTF2/TCH4 pin. The TIMA channel registers of the linked pair alternately control the output. Setting the MS4B bit in TIMA channel 4 status and control register (TASC4) links channel 4 and channel 5. The output compare value in the TIMA channel 4 registers initially controls the output on the Freescale Semiconductor MC68HC908AZ32A Data Sheet, Rev. 2 Functional Description 18 ...

Page 192

... The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the TIMA channel registers. 192 NOTE OVERFLOW PERIOD PULSE WIDTH OUTPUT OUTPUT COMPARE COMPARE 18.8.1 TIMA Status and Control MC68HC908AZ32A Data Sheet, Rev. 2 OVERFLOW OUTPUT COMPARE Register). 18.3.4 Pulse Width Freescale Semiconductor ...

Page 193

... TASC2 controls and monitors the buffered PWM function and TIMA channel 3 status and control register (TASC3) is unused. While the MS2B bit is set, the channel 3 pin, PTF1/TCH3, is available as a general-purpose I/O pin. Freescale Semiconductor NOTE MC68HC908AZ32A Data Sheet, Rev. 2 ...

Page 194

... PWM signal generation when changing the PWM pulse width to a new, much larger value the TIMA status control register (TASC) clear the TIMA stop bit, TSTOP. 194 NOTE Table 18-2). NOTE MC68HC908AZ32A Data Sheet, Rev. 2 Table 18-2). Freescale Semiconductor ...

Page 195

... Stop Mode The TIMA is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIMA counter. TIMA operation resumes when the MCU exits stop mode. Freescale Semiconductor Registers). MC68HC908AZ32A Data Sheet, Rev. 2 Interrupts ...

Page 196

... Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTE2/TCH0, PTF0/TACH2 and PTF2/TCH4 can be configured as buffered output compare or buffered PWM pins. 196 7.7.3 SIM Break Flag Control 18.8.1 TIMA Status and Control 1 ------------------------------------ - + t SU bus frequency MC68HC908AZ32A Data Sheet, Rev. 2 Register). Register). The minimum TCLK pulse Freescale Semiconductor ...

Page 197

... TIMA counter has not reached modulo value. TOIE — TIMA Overflow Interrupt Enable Bit This read/write bit enables TIMA overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit TIMA overflow interrupts enabled 0 = TIMA overflow interrupts disabled Freescale Semiconductor ...

Page 198

... Table 18-1. Prescaler Selection TIMA Clock Source Internal Bus Clock ÷1 Internal Bus Clock ÷ 2 Internal Bus Clock ÷ 4 Internal Bus Clock ÷ 8 Internal Bus Clock ÷ 16 Internal Bus Clock ÷ 32 Internal Bus Clock ÷ 64 PTD6/ATD14/TCLK MC68HC908AZ32A Data Sheet, Rev. 2 Freescale Semiconductor ...

Page 199

... Write: Reset: 1 Register Name and Address Bit 7 Read: BIT 7 Write: Reset: 1 Figure 18-6. TIMA Counter Modulo Registers (TAMODH and TAMODL) Reset the TIMA counter before writing to the TIMA counter modulo registers. Freescale Semiconductor NOTE TACNTH — $0022 BIT 14 BIT 13 BIT 12 BIT 11 R ...

Page 200

... MS2A ELS2B TASC3 — $002F CH3IE MS3A ELS3B Reserved Figure 18-7. TIMA Channel Status and Control Registers (TASC0–TASC5) MC68HC908AZ32A Data Sheet, Rev Bit 0 ELS0A TOV0 CH0MAX Bit 0 ELS1A TOV1 CH1MAX Bit 0 ELS2A TOV2 CH2MAX Bit 0 ELS3A TOV3 CH3MAX Freescale Semiconductor ...

Related keywords