MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 115

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MC908AZ32ACFU

Manufacturer Part Number
MC908AZ32ACFU
Description
IC MCU 32K FLASH 8.4MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908AZ32ACFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
40
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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11.4.1 Wait Mode
If enabled, the break module is active in wait mode. The SIM break wait bit (BW) in the SIM break status
register indicates whether wait was exited by a break interrupt. If so, the user can modify the return
address on the stack by subtracting one from it. See
11.4.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect break module register
states.
11.5 Break Module Registers
These registers control and monitor operation of the break module:
11.5.1 Break Status and Control Register
The break status and control register contains break module enable and status bits.
BRKE — Break Enable Bit
BRKA — Break Active Bit
Freescale Semiconductor
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic
0 to bit 7. Reset clears the BRKE bit.
This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to
BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
1 = (When read) Break address match
0 = (When read) No break address match
Break address register high (BRKH)
Break address register low (BRKL)
Break status and control register (BSCR)
Address:
Reset:
Read:
Write:
Figure 11-3. Break Status and Control Register (BSCR)
$FE0B
BRKE
Bit 7
0
= Unimplemented
BRKA
6
0
MC68HC908AZ32A Data Sheet, Rev. 2
5
0
0
4
0
0
7.7.1 SIM Break Status
3
0
0
2
0
0
Register.
1
0
0
Break Module Registers
Bit 0
0
0
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