MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 119

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MC908AZ32ACFU

Manufacturer Part Number
MC908AZ32ACFU
Description
IC MCU 32K FLASH 8.4MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908AZ32ACFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
40
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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12.3.1 Entering Monitor Mode
Table 12-1
Enter monitor mode by either
Once out of reset, the MCU waits for the host to send eight security bytes (see
security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host computer, indicating
that it is ready to receive a command.
Monitor mode uses alternate vectors for reset, SWI and break interrupt. The alternate vectors are in the
$FE page instead of the $FF page and allow code execution from the internal monitor firmware instead
of user code. The COP module is disabled in monitor mode as long as V
Electrical
Integration Module (SIM)
Table 12-2
Freescale Semiconductor
Executing a software interrupt instruction (SWI) or
Applying a logic 0 and then a logic 1 to the RST pin.
1. If the high voltage (V
IRQ1
V
V
Characteristics), is applied to either the IRQ1 pin or the RESET pin. (See
Monitor
Pin
Modes
1. For V
HI
HI
User
serts its COP enable output. The COP is enabled or disabled by the COPD bit in the configuration reg-
ister. (see
shows the pin conditions for entering monitor mode.
is a summary of the differences between user mode and monitor mode.
(1)
(1)
Holding the PTC3 pin low when entering monitor mode causes a bypass of
a divide-by-two stage at the oscillator. The CGMOUT frequency is equal to
the CGMXCLK frequency, and the OSC1 input directly generates internal
bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at
maximum bus frequency.
PTC0
HI
Pin
,
1
1
25.1.4 5.0 Volt DC Electrical
25.1.4 5.0 Volt DC Electrical
Disabled
Enabled
COP
PTC1
Pin
for more information on modes of operation).
0
0
HI
(1)
) is removed from the IRQ and/or RESET pin while in monitor mode, the SIM as-
PTA0
Pin
1
1
Vector
$FEFE
MC68HC908AZ32A Data Sheet, Rev. 2
$FFFE
Reset
High
Table 12-2. Mode Differences
Table 12-1. Mode Selection
PTC3
Pin
1
0
Characteristics, and
Characteristics).
Vector
$FFFF
$FEFF
Reset
Low
Monitor
Monitor
Mode
NOTE
Functions
$FEFC
Vector
$FFFC
Break
High
CGMXCLK
---------------------------- -
25.1.1 Maximum
2
CGMXCLK
CGMOUT
$FEFD
Vector
$FFFD
Break
Low
or
CGMVCLK
---------------------------- -
HI
Ratings.
(see
2
Vector
$FFFC
$FEFC
12.3.7
High
SWI
25.1.4 5.0 Volt DC
Functional Description
Chapter 7 System
Security). After the
Frequency
CGMOUT
------------------------- -
CGMOUT
------------------------- -
Bus
Vector
$FFFD
$FEFD
2
2
Low
SWI
119

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