MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 160

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MC908AZ32ACFU

Manufacturer Part Number
MC908AZ32ACFU
Description
IC MCU 32K FLASH 8.4MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908AZ32ACFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
40
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Serial Communications Interface (SCI)
OR — Receiver Overrun Bit
Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing
sequence.
by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit because OR
was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence
reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is important to know which byte is lost
due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after reading
the data register.
NF — Receiver Noise Flag Bit
160
receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after
the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition
can set the IDLE bit. Reset clears the IDLE bit.
This clearable, read-only bit is set when software fails to read the SCDR before the receive shift
register receives the next character. The OR bit generates an SCI error CPU interrupt request if the
ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is
not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears
the OR bit.
This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an NF
CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then
reading the SCDR. Reset clears the NF bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
1 = Noise detected
0 = No noise detected
Figure 16-15
BYTE 1
BYTE 1
shows the normal flag-clearing sequence and an example of an overrun caused
READ SCS1
READ SCDR
SCRF = 1
Figure 16-15. Flag Clearing Sequence
BYTE 1
OR = 0
MC68HC908AZ32A Data Sheet, Rev. 2
READ SCDR
READ SCS1
DELAYED FLAG CLEARING SEQUENCE
NORMAL FLAG CLEARING SEQUENCE
BYTE 2
BYTE 2
SCRF = 1
BYTE 1
OR = 0
READ SCDR
READ SCS1
SCRF = 1
BYTE 2
OR = 0
BYTE 3
BYTE 3
READ SCDR
READ SCDR
READ SCS1
READ SCS1
SCRF = 1
SCRF = 1
BYTE 3
BYTE 3
OR = 1
OR = 0
BYTE 4
BYTE 4
Freescale Semiconductor

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