MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 202

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MC908AZ32ACFU

Manufacturer Part Number
MC908AZ32ACFU
Description
IC MCU 32K FLASH 8.4MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908AZ32ACFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
40
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Timer Interface Module A (TIMA)
MSxA — Mode Select Bit A
ELSxB and ELSxA — Edge/Level Select Bits
202
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation. See
When ELSxB:A = 00, this read/write bit selects the initial output level of the TACHx pin once PWM,
output compare mode or input capture mode is enabled. See
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to port E or port F and pin
PTEx/TACHx or pin PTFx/TACHx is available as a general-purpose I/O pin. However, channel x is at
a state determined by these bits and becomes transparent to the respective pin when PWM, input
capture mode or output compare operation mode is enabled.
ELSxA work. Reset clears the ELSxB and ELSxA bits.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
1 = Initial output level low
0 = Initial output level high
MSxB:MSxA
X0
X1
1X
1X
1X
00
00
00
01
01
01
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIMA status and control register (TASC).
Before enabling a TIMA channel register for input capture operation, make
sure that the PTEx/TACHx pin or PTFx/TACHx pin is stable for at least two
bus clocks.
ELSxB:ELSxA
Table 18-2. Mode, Edge, and Level Selection
00
00
01
10
11
01
10
11
01
10
11
Table
MC68HC908AZ32A Data Sheet, Rev. 2
18-2.
Buffered Output
Buffered PWM
Output Preset
Input Capture
Compare or
Compare
or PWM
Output
Mode
NOTE
NOTE
Pin under Port Control;
Initialize Timer
Output Level High
Pin under Port Control;
Initialize Timer
Output Level Low
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
Table 18-2
Table
18-2. Reset clears the MSxA bit.
Configuration
shows how ELSxB and
Freescale Semiconductor

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