MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 212

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MC908AZ32ACFU

Manufacturer Part Number
MC908AZ32ACFU
Description
IC MCU 32K FLASH 8.4MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908AZ32ACFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
40
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Timer Interface Module B (TIMB)
19.3.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the PTF4 pin.
The TIMB channel registers of the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and
channel 1. The TIMB channel 0 registers initially control the pulse width on the PTF4 pin. Writing to the
TIMB channel 1 registers enables the TIMB channel 1 registers to synchronously control the pulse width
at the beginning of the next PWM period. At each subsequent overflow, the TIMB channel registers (0
or 1) that control the pulse width are the ones written to last. TBSC0 controls and monitors the buffered
PWM function, and TIMB channel 1 status and control register (TBSC1) is unused. While the MS0B bit is
set, the channel 1 pin, PTF5/TBCH1, is available as a general-purpose I/O pin.
19.3.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
212
1. In the TIMB status and control register (TBSC):
2. In the TIMB counter modulo registers (TBMODH–TBMODL) write the value for the required PWM
3. In the TIMB channel x registers (TBCHxH–TBCHxL) write the value for the required pulse width.
4. In TIMB channel x status and control register (TBSCx):
5. In the TIMB status control register (TBSC) clear the TIMB stop bit, TSTOP.
period.
a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP.
b. Reset the TIMB counter and prescaler by setting the TIMB reset bit, TRST.
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level
or PWM signals) to the mode select bits, MSxB–MSxA (see
select bits, ELSxB–ELSxA. The output action on compare must force the output to the
complement of the pulse width level (see
event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
MC68HC908AZ32A Data Sheet, Rev. 2
NOTE
NOTE
Table
19-2).
Table
19-2).
Freescale Semiconductor

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