MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 244

• Manufacturer Part Number: MC908AZ32ACFU
• Description: IC MCU 32K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ32ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

I/O Ports
23.2 Port A
Port A is an 8-bit general-purpose bidirectional I/O port.
23.2.1 Port A Data Register
The port A data register contains a data latch for each of the eight port A pins.
PTA[7:0] — Port A Data Bits
23.2.2 Data Direction Register A
Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to
a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer.
DDRA[7:0] — Data Direction Register A Bits
Figure 23-4
244
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
shows the port A I/O logic.
Address:
Address:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Reset:
Reset:
Read:
Read:
Write:
Write:
DDRA7
$0000
$0004
PTA7
Bit 7
Bit 7
0
Figure 23-3. Data Direction Register A (DDRA)
Figure 23-2. Port A Data Register (PTA)
DDRA6
PTA6
6
6
0
MC68HC908AZ32A Data Sheet, Rev. 2
DDRA5
PTA5
5
5
0
NOTE
DDRA4
Unaffected by Reset
PTA4
4
4
0
DDRA3
PTA3
3
3
0
DDRA2
PTA2
2
2
0
DDRA1
PTA1
1
1
0
Freescale Semiconductor
DDRA0
PTA0
Bit 0
Bit 0
0