MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 253

• Manufacturer Part Number: MC908AZ32ACFU
• Description: IC MCU 32K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ32ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TACH[1:0] — Timer Channel I/O Bits
RxD — SCI Receive Data Input Bit
TxD — SCI Transmit Data Output
23.6.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to
a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer.
DDRE[7:0] — Data Direction Register E Bits
Freescale Semiconductor
The PTE3/TCH1–PTE2/TCH0 pins are the TIM input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTE3/TCH1–PTE2/TCH0 pins are timer channel I/O
pins or general-purpose I/O pins. (See
The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. (See
16.8.1 SCI Control Register
The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. (See
16.8.1 SCI Control Register
These read/write bits control port E data direction. Reset clears DDRE[7:0], configuring all port E pins
as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
Address:
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the TIM. However, the DDRE bits always
determine whether reading port E returns the states of the latches or the
states of the pins. (See
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the SCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. (See
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Reset:
Read:
Write:
DDRE7
$000C
Bit 7
0
Figure 23-15. Data Direction Register E (DDRE)
1).
1).
DDRE6
6
0
MC68HC908AZ32A Data Sheet, Rev. 2
Table
DDRE5
18.8.4 TIMA Channel Status and Control
5
0
23-5).
Table
NOTE
NOTE
NOTE
DDRE4
23-5).
4
0
DDRE3
3
0
DDRE2
2
0
DDRE1
1
0
Registers).
DDRE0
Bit 0
0
Port E
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