MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 295

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MC908AZ32ACFU

Manufacturer Part Number
MC908AZ32ACFU
Description
IC MCU 32K FLASH 8.4MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908AZ32ACFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
40
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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24.13.13 MSCAN08 Identifier Mask Registers (CIDMR0–3)
The identifier mask registers specify which of the corresponding bits in the identifier acceptance register
are relevant for acceptance filtering. For standard identifiers it is required to program the last three bits
(AM2-AM0) in the mask register CIDMR1 to ‘don’t care’.
AM7–AM0 — Acceptance Mask Bits
Freescale Semiconductor
If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier
acceptance register must be the same as its identifier bit before a match will be detected. The message
will be accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit
in the identifier acceptance register will not affect whether or not the message is accepted.
1 = Ignore corresponding acceptance code register bit.
0 = Match corresponding acceptance code register and identifier bits.
CIDMRO
CIDMR1
CIDMR2
CIDMR3
The CIDMR0-3 registers can be written only if the SFTRES bit in the
CMCR0 is set
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Figure 24-27. Identifier Mask Registers (CIDMR0–CIDMR3)
AM7
AM7
AM7
AM7
Bit 7
Bit 7
Bit 7
Bit 7
Address: $0514
Address: $0515
Address: $0516
Address: $0517
AM6
AM6
AM6
AM6
6
6
6
6
MC68HC908AZ32A Data Sheet, Rev. 2
AM5
AM5
AM5
AM5
5
5
5
5
NOTE
Unaffected by Reset
Unaffected by Reset
Unaffected by Reset
Unaffected by Reset
AM4
AM4
AM4
AM4
4
4
4
4
AM3
AM3
AM3
AM3
3
3
3
3
Programmer’s Model of Control Registers
AM2
AM2
AM2
AM2
2
2
2
2
AM1
AM1
AM1
AM1
1
1
1
1
Bit 0
AM0
Bit 0
AM0
Bit 0
AM0
Bit 0
AM0
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