MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 45

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MC908AZ32ACFU

Manufacturer Part Number
MC908AZ32ACFU
Description
IC MCU 32K FLASH 8.4MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908AZ32ACFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
40
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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4.3.2 FLASH Block Protect Register
The FLASH Block Protect Register (FLBPR) is implemented as a byte within the FLASH memory and
therefore can only be written during a FLASH programming sequence. The value in this register
determines the starting location of the protected range within the FLASH memory.
FLBPR[7:0] — Block Protect Register Bit7 to Bit0
FLASH Protected Ranges:
Freescale Semiconductor
These eight bits represent bits [14:7] of a 16-bit memory address. Bit-15 is logic 1 and bits [6:0] are
logic 0s.
The resultant 16-bit address is used for specifying the start address of the FLASH memory for block
protection. FLASH is protected from this start address to the end of FLASH memory at $FFFF. With
this mechanism, the protect start address can be $XX00 and $XX80 (128 byte page boundaries) within
the FLASH array.
Address:
Read:
Write:
Start address of FLASH block protect
$FF80
BPR7
Bit 7
Figure 4-2. FLASH Block Protect Register (FLBPR)
Figure 4-3. FLASH Block Protect Start Address
FLBPR[7:0]
$FF
$FE
$FD
$0B
$0A
$09
$08
$04
$03
$02
$01
$00
BPR6
6
MC68HC908AZ32A Data Sheet, Rev. 2
BPR5
5
1
BPR4
4
FLBPR value
Protected Range
$FE80 – $FFFF
$FF00 – $FFFF
$8580 – $FFFF
$8500 – $FFFF
$8480 – $FFFF
$8400 – $FFFF
$8200 – $FFFF
$8180 – $FFFF
$8100 – $FFFF
$8080 – $FFFF
$8000 – $FFFF
16-bit memory address
No Protection
BPR3
3
FLASH Control and Block Protect Registers
BPR2
0 0 0 0 0 0 0
2
BPR1
1
BPR0
Bit 0
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