MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 93

• Manufacturer Part Number: MC908AZ32ACFU
• Description: IC MCU 32K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ32ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
8.3.2.1 Circuits
The PLL consists of these circuits:
The operating range of the VCO is programmable for a wide range of frequencies and for maximum
immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
CGMXFC pin changes the frequency within this range. By design, f
center-of-range frequency, f
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency,
f
running at a frequency f
The VCO’s output clock, CGMVCLK, running at a frequency f
programmable modulo divider. The modulo divider reduces the VCO clock by a factor, N. The divider’s
output is the VCO feedback clock, CGMVDV, running at a frequency f
Programming the PLL
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock,
CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The
Freescale Semiconductor
CGMRCLK
PLL Bandwidth Control Register
•
•
•
•
•
PLL Programming Register
Register Name
Voltage-controlled oscillator (VCO)
Modulo VCO frequency divider
Phase detector
Loop filter
Lock detector
PLL Control Register
, and is fed to the PLL through a buffer. The buffer output is the final reference clock, CGMRDV,
(PBWC)
(PCTL)
(PPG)
for more information.
CGMRDV
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
NOM
Register
Address
Table 8-1. I/O Register Address Summary
AUTO
, (4.9152 MHz) times a linear factor L or (L)f
Bit 7
PLLIE
MUL7
= f
0
0
0
Figure 8-2. I/O Register Summary
CGMRCLK
MC68HC908AZ32A Data Sheet, Rev. 2
= Unimplemented
LOCK
MUL6
PLLF
$001C
PCTL
6
0
0
1
.
PLLON
MUL5
ACQ
5
1
0
1
PBWC
$001D
MUL4
BCS
XLD
CGMVCLK
4
0
0
0
CGMVRS
CGMVRS
$001E
PPG
CGMVDV
VRS7
. Modulating the voltage on the
, is fed back through a
3
1
1
0
0
0
is equal to the nominal
NOM
= f
VRS6
CGMVCLK
2
1
1
0
0
1
.
Functional Description
VRS5
/N. See
1
1
1
0
0
1
8.3.2.4
Bit 0
VRS4
1
1
0
0
0
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