MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 94

• Manufacturer Part Number: MC908AZ32ACFU
• Description: IC MCU 32K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ32ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Clock Generator Module (CGM)
loop filter then slightly alters the dc voltage on the external capacitor connected to CGMXFC based on
the width and direction of the correction pulse. The filter can make fast or slow corrections depending on
its mode, as described in
the reference frequency determines the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final
reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final
reference frequency, f
on this comparison.
8.3.2.2 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
8.3.2.3 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. See
Bandwidth Control
CPU interrupt request and then check the LOCK bit. If CPU interrupts are disabled, software can poll the
LOCK bit continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK
bit is set, the VCO clock is safe to use as the source for the base clock. See
Circuit. If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has
suffered a severe noise hit and the software must take appropriate action, depending on the application.
See
These conditions apply when the PLL is in automatic bandwidth control mode:
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8.6
Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the
VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in
the PLL bandwidth control register. See
Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected
as the base clock source. See
tracking mode when it’s not in acquisition mode or when the ACQ bit is set.
The ACQ bit (see
filter. See
The ACQ bit is set when the VCO frequency is within a certain tolerance, Δ
the VCO frequency is out of a certain tolerance, Δ
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within a certain tolerance, Δ
when the VCO frequency is out of a certain tolerance, Δ
Specifications.
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. See
Interrupts.
8.3.2.2 Acquisition and Tracking
Register. If PLL CPU interrupt requests are enabled, the software can wait for a PLL
CGMRDV
8.5.2 PLL Bandwidth Control
8.3.2.2 Acquisition and Tracking
8.5.1 PLL Control
. The circuit determines the mode of the PLL and the lock condition based
MC68HC908AZ32A Data Sheet, Rev. 2
8.3.3 Base Clock Selector
Register.
8.5.2 PLL Bandwidth Control
Modes.
Register) is a read-only indicator of the mode of the
unt
Modes. The value of the external capacitor and
. See
unl
Circuit. The PLL is automatically in
Chapter 25 Electrical
. See
Chapter 25 Electrical
Register.
8.3.3 Base Clock Selector
trk
, and is cleared when
Lock
Freescale Semiconductor
Specifications.
, and is cleared
8.5.2 PLL