HD6412332VFCBL25 Renesas Electronics America, HD6412332VFCBL25 Datasheet - Page 252
HD6412332VFCBL25
Manufacturer Part Number
HD6412332VFCBL25
Description
IC H8S MCU ROMLESS 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD6412332VFCBL25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Section 2 Instruction Descriptions
2.2.65 (3)
SUB (SUBtract binary)
Operation
ERd – (EAs)
Assembly-Language Format
SUB.L <EAs>, ERd
Operand Size
Longword
Description
This instruction subtracts a source operand from the contents of a 32-bit register ERd (destination
operand) and stores the result in the 32-bit register ERd.
Available Registers
ERd: ER0 to ER7
ERs: ER0 to ER7
Operand Format and Number of States Required for Execution
Notes
Rev. 4.00 Feb 24, 2006 page 236 of 322
REJ09B0139-0400
Immediate
Register direct
Addressing
Mode
SUB (L)
Mnemonic
ERd
SUB.L
SUB.L
#xx:32, ERd
Operands
ERs, ERd
1st byte
7
1
A
A
1 ers 0 erd
2nd byte
3
0 erd
Condition Code
H: Set to 1 if there is a borrow at bit 27;
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Set to 1 if there is a borrow at bit 31;
3rd byte
Instruction Format
otherwise cleared to 0.
cleared to 0.
cleared to 0.
cleared to 0.
otherwise cleared to 0.
—
I
UI H
—
4th byte
—
IMM
U
5th byte
N
Subtract Binary
Z
6th byte
V
C
States
No. of
3
1
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