HD64F2134FA20 Renesas Electronics America, HD64F2134FA20 Datasheet - Page 689
HD64F2134FA20
Manufacturer Part Number
HD64F2134FA20
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2134FA20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Part Number:
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Quantity:
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22.5
22.5.1
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode is entered by setting SWE to 1. Program mode is entered by setting SWE to
1, then setting the PSU bit in FLMCR2, and finally setting the P bit. Erase mode is entered by
setting SWE to 1, then setting the ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is
initialized to H'80 by a reset, and in hardware standby mode, software standby mode, subactive
mode, subsleep mode, and watch mode. When on-chip flash memory is disabled, a read will return
H'00, and writes are invalid.
Writes to the EV and PV bits in FLMCR1 are enabled only when SWE=1; writes to the E bit only
when SWE = 1, and ESU = 1; and writes to the P bit only when SWE = 1, and PSU = 1.
Bit 7—Flash Write Enable (FWE): Sets hardware protection against flash memory
programming/erasing. This bit cannot be modified and is always read as 1.
Bit 6—Software Write Enable (SWE): Enables or disables flash memory programming. SWE
should be set before setting bits ESU, PSU, EV, PV, E, P, and EB7 to EB0, and should not be
cleared at the same time as these bits.
Bit 5 and 4—Reserved: These bits cannot be modified and are always read as 0.
Bit 6
SWE
0
1
Bit
Initial value
Read/Write
Register Descriptions
Flash Memory Control Register 1 (FLMCR1)
Description
Writes disabled
Writes enabled
Section 22 ROM
FWE
R
7
1
SWE
R/W
6
0
(H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version)
—
—
5
0
—
—
4
0
Rev. 4.00 Jun 06, 2006 page 633 of 1004
R/W
EV
3
0
R/W
PV
2
0
REJ09B0301-0400
R/W
E
1
0
(Initial value)
R/W
P
0
0
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