HD64F3684FP Renesas Electronics America, HD64F3684FP Datasheet - Page 100

• Manufacturer Part Number: HD64F3684FP
• Description: IC H8 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3684FP

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 4 Address Break
4.1.4
BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break
interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8-
bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for
even and odd addresses in the data transmission. Therefore, comparison data must be set in
BDRH for byte access. For word access, the data bus used depends on the address. See section
4.1.1, Address Break Control Register (ABRKCR), for details. The initial value of this register is
undefined.
4.2
When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an
interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the
address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt
request is accepted, interrupt exception handling starts after the instruction being executed ends.
The address break interrupt is not masked by the I bit in CCR of the CPU.
Figures 4.2 show the operation examples of the address break interrupt setting.
Rev.5.00 Nov. 02, 2005 Page 66 of 500
REJ09B0027-0500
When the address break is specified in instruction execution cycle
Break Data Registers (BDRH, BDRL)
Operation
Register setting
• ABRKCR = H'80
• BAR = H'025A
Address
bus
Interrupt
request
Figure 4.2 Address Break Interrupt Operation Example (1)
prefetch
instruc-
NOP
0258
tion
prefetch
instruc-
NOP
Program
*
tion
025A
0258
025A
025C
0260
0262
:
Interrupt acceptance
prefetch
instruc-
tion 1
NOP
NOP
MOV.W @H'025A,R0
NOP
NOP
MOV
025C
:
prefetch
instruc-
tion 2
MOV
025E
processing
Internal
Underline indicates the address
to be stacked.
SP-2
Stack save
SP-4