HD64F3684FP Renesas Electronics America, HD64F3684FP Datasheet - Page 12

IC H8 MCU FLASH 32K 64LQFP

HD64F3684FP

Manufacturer Part Number
HD64F3684FP
Description
IC H8 MCU FLASH 32K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3684FP

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 1 Overview ............................................................................................... 1
1.1
1.2
1.3
1.4
Section 2 CPU ..................................................................................................... 11
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Section 3 Exception Handling ............................................................................. 47
3.1
3.2
Rev.5.00 Nov. 02, 2005 Page x of xxxii
Features.................................................................................................................................. 1
Internal Block Diagram.......................................................................................................... 3
Pin Arrangement .................................................................................................................... 5
Pin Functions ......................................................................................................................... 7
Address Space and Memory Map ........................................................................................ 12
Register Configuration......................................................................................................... 15
2.2.1
2.2.2
2.2.3
Data Formats........................................................................................................................ 19
2.3.1
2.3.2
Instruction Set ...................................................................................................................... 22
2.4.1
2.4.2
Addressing Modes and Effective Address Calculation........................................................ 33
2.5.1
2.5.2
Basic Bus Cycle ................................................................................................................... 38
2.6.1
2.6.2
CPU States ........................................................................................................................... 40
Usage Notes ......................................................................................................................... 41
2.8.1
2.8.2
2.8.3
Exception Sources and Vector Address ............................................................................... 48
Register Descriptions........................................................................................................... 49
3.2.1
3.2.2
3.2.3
3.2.4
General Registers.................................................................................................... 16
Program Counter (PC) ............................................................................................ 17
Condition-Code Register (CCR)............................................................................. 17
General Register Data Formats............................................................................... 19
Memory Data Formats ............................................................................................ 21
Table of Instructions Classified by Function .......................................................... 22
Basic Instruction Formats ....................................................................................... 32
Addressing Modes .................................................................................................. 33
Effective Address Calculation ................................................................................ 36
Access to On-Chip Memory (RAM, ROM)............................................................ 38
On-Chip Peripheral Modules .................................................................................. 39
Notes on Data Access to Empty Areas ................................................................... 41
EEPMOV Instruction.............................................................................................. 41
Bit-Manipulation Instruction .................................................................................. 41
Interrupt Edge Select Register 1 (IEGR1) .............................................................. 50
Interrupt Edge Select Register 2 (IEGR2) .............................................................. 51
Interrupt Enable Register 1 (IENR1) ...................................................................... 52
Interrupt Enable Register 2 (IENR2) ...................................................................... 53
Contents

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