HD64F3684FP Renesas Electronics America, HD64F3684FP Datasheet - Page 196

• Manufacturer Part Number: HD64F3684FP
• Description: IC H8 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3684FP

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 12 Timer V
TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match,
CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested.
Note that they must not be compared during the T3 state of a TCORA write cycle.
Timer output from the TMOV pin can be controlled by the identifying signal (compare match A)
and the settings of bits OS3 to OS0 in TCSRV.
TCORA and TCORB are initialized to H'FF.
12.3.3
TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV,
and controls each interrupt request.
Rev.5.00 Nov. 02, 2005 Page 162 of 500
REJ09B0027-0500
Bit
7
6
5
4
3
2
1
0
Bit Name
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
Timer Control Register V0 (TCRV0)
Initial
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Compare Match Interrupt Enable B
When this bit is set to 1, interrupt request from the CMFB
bit in TCSRV is enabled.
Compare Match Interrupt Enable A
When this bit is set to 1, interrupt request from the CMFA
bit in TCSRV is enabled.
Timer Overflow Interrupt Enable
When this bit is set to 1, interrupt request from the OVF
bit in TCSRV is enabled.
Counter Clear 1 and 0
These bits specify the clearing conditions of TCNTV.
00: Clearing is disabled
01: Cleared by compare match A
10: Cleared by compare match B
11: Cleared on the rising edge of the TMRIV pin. The
Clock Select 2 to 0
These bits select clock signals to input to TCNTV and the
counting condition in combination with ICKS0 in TCRV1.
Refer to table 12.2.
operation of TCNTV after clearing depends on TRGE
in TCRV1.