HD64F3684FP Renesas Electronics America, HD64F3684FP Datasheet - Page 206

IC H8 MCU FLASH 32K 64LQFP

HD64F3684FP

Manufacturer Part Number
HD64F3684FP
Description
IC H8 MCU FLASH 32K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3684FP

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 12 Timer V
12.6
The following types of contention or operation can occur in timer V operation.
1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear
2. If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write
3. If compare matches A and B occur simultaneously, any conflict between the output selections
4. Depending on the timing, TCNTV may be incremented by a switch between different internal
Rev.5.00 Nov. 02, 2005 Page 172 of 500
REJ09B0027-0500
signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 12.11, clearing
takes precedence and the write to the counter is not carried out. If counting-up is generated in
the T3 state of a TCNTV write cycle, writing takes precedence.
to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure
12.12 shows the timing.
for compare match A and compare match B is resolved by the following priority: toggle
output output 1 output 0.
clock sources. When TCNTV is internally clocked, an increment pulse is generated from the
falling edge of an internal clock signal, that is divided system clock ( ). Therefore, as shown
in figure 12.3 the switch is from a high clock signal to a low clock signal, the switchover is
seen as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a
switch between internal and external clocks.
Usage Notes
Figure 12.11 Contention between TCNTV Write and Clear
Counter clear signal
Internal write signal
Address
TCNTV
TCNTV write cycle by CPU
T
1
TCNTV address
N
T
2
T
3
H'00

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