HD64F3684FP Renesas Electronics America, HD64F3684FP Datasheet - Page 228

• Manufacturer Part Number: HD64F3684FP
• Description: IC H8 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3684FP

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 13 Timer Z
13.3.11 Timer Status Register (TSR)
TSR indicates generation of an overflow/underflow of TCNT and a compare match/input capture
of GRA, GRB, GRC, and GRD. These flags are interrupt sources. If an interrupt is enabled by a
corresponding bit in TIER, TSR requests an interrupt for the CPU. Timer Z has two TSR registers,
one for each channel.
Rev.5.00 Nov. 02, 2005 Page 194 of 500
REJ09B0027-0500
Bit
7, 6
5
4
3
Bit Name
UDF*
OVF
IMFD
Initial
value
All 1
0
0
0
R/W
R/W
R/W
R/W
Reserved
These bits are always read as 1.
Underflow Flag
[Setting condition]
[Clearing condition]
Overflow Flag
[Setting condition]
[Clearing condition]
Input Capture/Compare Match Flag D
[Setting conditions]
[Clearing condition]
Description
When TCNT_1 underflows
When 0 is written to UDF after reading UDF = 1
When the TCNT value underflows
When 0 is written to OVF after reading OVF = 1
When TCNT = GRD and GRD is functioning as output
compare register
When TCNT value is transferred to GRD by input
capture signal and GRD is functioning as input
capture register
When 0 is written to IMFD after reading IMFD = 1