HD64F3684FP Renesas Electronics America, HD64F3684FP Datasheet - Page 325

IC H8 MCU FLASH 32K 64LQFP

HD64F3684FP

Manufacturer Part Number
HD64F3684FP
Description
IC H8 MCU FLASH 32K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3684FP

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3684FPI
Quantity:
2 761
Part Number:
HD64F3684FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3684FPV
Manufacturer:
RENESAS
Quantity:
28
Part Number:
HD64F3684FPV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Figure 16.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Yes
No
No
Clear TE and RE bits in SCR to 0
Start transmission/reception
Write transmit data to TDR
Read receive data in RDR
Read TDRE flag in SSR
Read RDRF flag in SSR
Read OER flag in SSR
All data received?
TDRE = 1
RDRF = 1
OER = 1
<End>
Yes
Yes
No
No
(Clocked Synchronous Mode)
Error processing
Yes
[1]
[2]
[3]
[4]
Section 16 Serial Communication Interface 3 (SCI3)
[1] Read SSR and check that the TDRE
[2] Read SSR and check that the RDRF
[3] To continue serial transmission/
[4] If an overrun error occurs, read the
Rev.5.00 Nov. 02, 2005 Page 291 of 500
For overrun error processing, see
flag is set to 1, then write transmit
data to TDR.
TDRE flag is automatically cleared to
0.
flag is set to 1, then read the receive
data in RDR.
RDRF flag is automatically cleared to
0.
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading RDR.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible. Then write data to
TDR.
TDRE flag is automatically cleared to
0. When data is read from RDR, the
RDRF flag is automatically cleared to
0.
OER flag in SSR, and after
performing the appropriate error
processing, clear the OER flag to 0.
Transmission/reception cannot be
resumed if the OER flag is set to 1.
figure 16.13.
When data is written to TDR, the
When data is read from RDR, the
When data is written to TDR, the
REJ09B0027-0500

Related parts for HD64F3684FP