HD64F3684FP Renesas Electronics America, HD64F3684FP Datasheet - Page 340

• Manufacturer Part Number: HD64F3684FP
• Description: IC H8 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3684FP

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 17 I
17.3.1
ICCR1 enables or disables the I
master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Rev.5.00 Nov. 02, 2005 Page 306 of 500
REJ09B0027-0500
Bit
7
6
5
4
I
I
2
2
C bus receive data register (ICDRR)
C bus shift register (ICDRS)
Bit Name
ICE
RCVD
MST
TRS
I
2
2
C Bus Control Register 1 (ICCR1)
C Bus Interface 2 (IIC2)
Initial
Value
0
0
0
0
2
C bus interface 2, controls transmission or reception, and selects
R/W
R/W
R/W
R/W
R/W
Description
I
0: This module is halted. (SCL and SDA pins are set to
1: This bit is enabled for transfer operations. (SCL and
Reception Disable
This bit enables or disables the next operation when TRS
is 0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
Master/Slave Select
Transmit/Receive Select
In master mode with the I
is lost, MST and TRS are both reset by hardware,
causing a transition to slave receive mode. Modification
of the TRS bit should be made between transfer frames.
After data receive has been started in slave receive
mode, when the first seven bits of the receive data agree
with the slave address that is set to SAR and the eighth
bit is 1, TRS is automatically set to 1. If an overrun error
occurs in master mode with the clock synchronous serial
format, MST is cleared to 0 and slave receive mode is
entered.
Operating modes are described below according to MST
and TRS combination. When clocked synchronous serial
format is selected and MST is 1, clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
2
C Bus Interface Enable
port function.)
SDA pins are bus drive state.)
2
C bus format, when arbitration