HD64F3684FP Renesas Electronics America, HD64F3684FP Datasheet - Page 77

• Manufacturer Part Number: HD64F3684FP
• Description: IC H8 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3684FP

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

1. When the BSET instruction is executed, first the CPU reads port 5.
2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction.
Input/output
Pin state
PCR5
PDR5
Input/output
Pin state
PCR5
PDR5
BSET
Prior to executing BSET instruction
BSET instruction executed instruction
After executing BSET instruction
Description on operation
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level
input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level
signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem,
store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the
data in the work area, then write this data to PDR5.
#0,
P57
Input
Low
level
0
1
P57
Input
Low
level
0
0
@PDR5
0
0
0
P56
Input
High
level
P56
Input
High
level
1
P55
Output
Low
level
1
0
P55
Output
Low
level
1
0
The BSET instruction is executed for port 5.
P54
Output
Low
level
1
0
P54
Output
Low
level
1
0
P53
Output
Low
level
1
0
P53
Output
Low
level
1
0
Rev.5.00 Nov. 02, 2005 Page 43 of 500
P52
Output
Low
level
1
0
P52
Output
Low
level
1
0
P51
Output
Low
level
1
0
P51
Output
Low
level
1
0
REJ09B0027-0500
Section 2 CPU
P50
Output
Low
level
1
0
P50
Output
High
level
1
1