HD64F3684FP Renesas Electronics America, HD64F3684FP Datasheet - Page 79

IC H8 MCU FLASH 32K 64LQFP

HD64F3684FP

Manufacturer Part Number
HD64F3684FP
Description
IC H8 MCU FLASH 32K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3684FP

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only
2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE.
3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends.
Input/output
Pin state
PCR5
PDR5
Input/output
Pin state
PCR5
PDR5
BCLR
Prior to executing BCLR instruction
BCLR instruction executed
After executing BCLR instruction
Description on operation
register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F.
As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However,
bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins.
To prevent this problem, store a copy of the PDR5 data in a work area in memory and
manipulate data of the bit in the work area, then write this data to PDR5.
#0,
P57
Input
Low
level
0
1
P57
Output
Low
level
1
1
@PCR5
0
0
0
P56
Input
High
level
P56
Output
High
level
1
P55
Output
Low
level
1
0
P55
Low
level
1
0
Output
The BCLR instruction is executed for PCR5.
P54
Output
Low
level
1
0
P54
Output
Low
level
1
0
P53
Output
Low
level
1
0
P53
Output
Low
level
1
0
Rev.5.00 Nov. 02, 2005 Page 45 of 500
P52
Output
Low
level
1
0
P52
Output
Low
level
1
0
P51
Output
Low
level
1
0
P51
Output
Low
level
1
0
REJ09B0027-0500
Section 2 CPU
P50
Output
Low
level
1
0
P50
Input
High
level
0
0

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