HD64F3684FP Renesas Electronics America, HD64F3684FP Datasheet - Page 99

• Manufacturer Part Number: HD64F3684FP
• Description: IC H8 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3684FP

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

When an address break is set in the data read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 4.1 shows the access and
data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a
byte access is generated twice. For details on data widths of each register, see section 22.1,
Register Addresses (Address Order).
Table 4.1
4.1.2
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
4.1.3
BARH and BARL are 16-bit read/write registers that set the address for generating an address
break interrupt. When setting the address break condition to the instruction execution cycle, set
the first byte address of the instruction. The initial value of this register is H'FFFF.
ROM space
RAM space
I/O register with 8-bit data
bus width
I/O register with 16-bit data
bus width
Bit
7
6
5 to 0
Bit Name
ABIF
ABIE
Address Break Status Register (ABRKSR)
Break Address Registers (BARH, BARL)
Access and Data Bus Used
Initial
Value
0
0
All 1
Even Address Odd Address
Upper 8 bits
Upper 8 bits
Upper 8 bits
Upper 8 bits
R/W
R/W
R/W
Word Access
Description
Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR is satisfied
[Clearing condition]
When 0 is written after ABIF=1 is read
Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
Reserved
These bits are always read as 1.
Lower 8 bits
Lower 8 bits
Upper 8 bits
Lower 8 bits
Rev.5.00 Nov. 02, 2005 Page 65 of 500
Upper 8 bits
Upper 8 bits
Even Address Odd Address
Upper 8 bits
Byte Access
Section 4 Address Break
REJ09B0027-0500
Upper 8 bits
Upper 8 bits
Upper 8 bits