MC68HC908LB8CPE Freescale Semiconductor, MC68HC908LB8CPE Datasheet - Page 121
MC68HC908LB8CPE
Manufacturer Part Number
MC68HC908LB8CPE
Description
IC MCU 8K FLASH 8MHZ 20DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC908LB8CDWE.pdf
(234 pages)
Specifications of MC68HC908LB8CPE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVR, POR, PWM
Number Of I /o
18
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908LB8CPE
Manufacturer:
IR
Quantity:
10
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12.4 LVI Status Register
The LVI status register (LVISR) indicates if the V
LVI resets have been disabled.
LVIOUT — LVI Output Bit
12.5 LVI Interrupts
The LVI module does not generate interrupt requests.
12.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power- consumption standby modes.
12.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
12.6.2 Stop Mode
When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration
register is set, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module
can generate a reset and bring the MCU out of stop mode.
Freescale Semiconductor
This read-only flag becomes set when the V
when V
that prevents oscillation into and out of reset (see
DD
voltage rises above V
Address: $FE0C
Reset:
Read:
Write:
LVIOUT
Bit 7
0
= Unimplemented
Figure 12-2. LVI Status Register (LVISR)
V
TRIPF
6
0
0
V
Table 12-1. LVIOUT Bit Indication
V
TRIPR
DD
DD
< V
MC68HC908LB8 Data Sheet, Rev. 1
V
> V
< V
DD
DD
. The difference in these threshold levels results in a hysteresis
TRIPR
TRIPF
< V
5
0
0
TRIPR
DD
DD
voltage falls below the V
4
0
0
voltage was detected below the V
Table
Previous value
12-1). Reset clears the LVIOUT bit.
R
3
0
0
LVIOUT
0
1
= Reserved
2
0
0
TRIPF
1
0
0
trip voltage and is cleared
TRIPF
Bit 0
LVI Status Register
R
0
level while
121
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