MC68HC908LB8CPE Freescale Semiconductor, MC68HC908LB8CPE Datasheet - Page 205
MC68HC908LB8CPE
Manufacturer Part Number
MC68HC908LB8CPE
Description
IC MCU 8K FLASH 8MHZ 20DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC908LB8CDWE.pdf
(234 pages)
Specifications of MC68HC908LB8CPE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVR, POR, PWM
Number Of I /o
18
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908LB8CPE
Manufacturer:
IR
Quantity:
10
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19.2.1.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
19.2.1.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
19.2.1.4 COP During Break Interrupts
The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary
register (BRKAR).
19.2.2 Break Module Registers
These registers control and monitor operation of the break module:
19.2.2.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
BRKE — Break Enable Bit
BRKA — Break Active Bit
Freescale Semiconductor
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•
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This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit
7. Reset clears the BRKE bit.
This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA
generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset
clears the BRKA bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
1 = Break address match
0 = No break address match
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode)
Break status and control register (BRKSCR)
Break address register high (BRKH)
Break address register low (BRKL)
Break status register (BSR)
Break flag control register (BFCR)
Address: $FE0B
Reset:
Read:
Write:
Figure 19-3. Break Status and Control Register (BRKSCR)
BRKE
Bit 7
0
= Unimplemented
BRKA
6
0
MC68HC908LB8 Data Sheet, Rev. 1
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
Break Module (BRK)
Bit 0
0
0
205
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