MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 45
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MCHC11F1CFNE3
Manufacturer Part Number
MCHC11F1CFNE3
Description
IC MCU 8BIT 1K RAM 68-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Specifications of MCHC11F1CFNE3
Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
30
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
A/d Inputs
8-Channel, 8-Bit
Eeprom Memory
512 Bytes
Input Output
30
Interface
SCI/SPI
Memory Type
EPROM
Number Of Bits
8
Package Type
68-pin PLCC
Programmable Memory
0 Bytes
Timers
3-16-bit
Voltage, Range
3-5.5 V
Controller Family/series
68HC11
No. Of I/o's
30
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC11F
Core
HC11
Data Bus Width
8 bit
Program Memory Size
512 B
Data Ram Size
1 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
-
Lead Free Status / Rohs Status
RoHS Compliant part
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4.3.1 Mode Selection
TECHNICAL DATA
Notes:
1. Bits 1 and 0 can be written once only in first 64 cycles. When SMOD = 1, these bits can be written any time. All
2. Bits can be written to zero (protection disabled) once only in first 64 cycles or at any time in special modes. Bits
3. Bits 5, 4, 2, 1, and 0 can be written once only in first 64 cycles. When SMOD = 1, bits 5, 4, 2, 1, and 0 can be
4. Bit 5 (CLK4X) can be written only one time.
5. Bit 4 (IRV) can be written only one time.
6. Can be written once in first 64 cycles after reset in normal modes or at any time in special modes.
The four mode variations are selected by the logic levels present on the MODA and
MODB pins at the rising edge of RESET. The MODA and MODB logic levels determine
the logic state of SMOD and MDA control bits in the HPRIO register.
After reset is released, the mode select pins no longer influence the MCU operating
mode. In single-chip operating mode, the MODA pin is connected to a logic level zero.
In expanded mode, MODA should be connected to V
4.7 k . The MODA pin also functions as the load instruction register (LIR) pin when
the MCU is not in reset. The open-drain active low LIR output pin drives low during the
first E cycle of each instruction (opcode fetch). The MODB pin also functions as stand-
by power input (V
V
requirements.
Refer to Table 4-3, which is a summary of mode pin operation, the mode control bits,
and the four operating modes.
Register
Address
DD
other bits can be written at any time.
can be set to one at any time.
written at any time. All other bits can be written at any time
$x03C
$x03D
$x024
$x035
$x038
$x039
MODB
. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for V
1
1
0
0
Input Levels
at Reset
Timer Interrupt Mask 2 (TMSK2)
Block Protect Register (BPROT)
System Configuration Options 2 (OPT2)
System Configuration Options (OPTION)
Highest Priority I-bit and Miscellaneous (HPRIO)
RAM and I/O Map Register (INIT)
STBY
Table 4-3 Hardware Mode Select Summary
Table 4-2 Write Access Limited Registers
MODA
Freescale Semiconductor, Inc.
OPERATING MODES AND ON-CHIP MEMORY
0
1
0
1
For More Information On This Product,
), which allows RAM contents to be maintained in absence of
Register
Name
Go to: www.freescale.com
Special Bootstrap
Special Test
Single Chip
Expanded
Mode
Must be Written in
First 64 Cycles
RBOOT
DD
0
0
1
0
Note 1
Note 2
Note 3
through a pull-up resistor of
Yes
No
No
Control Bits in HPRIO
(Latched at Reset)
SMOD
0
0
1
1
Write One Time
STBY
Note 4
Note 5
Note 6
Only
—
—
—
MDA
voltage
0
1
0
1
4-7