MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 61

• Manufacturer Part Number: MCHC11F1CFNE3
• Description: IC MCU 8BIT 1K RAM 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MCHC11F1CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 30
• Interface: SCI/SPI
• Memory Type: EPROM
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 30
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11F
• Core: HC11
• Data Bus Width: 8 bit
• Program Memory Size: 512 B
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

TECHNICAL DATA
CSPROG
CSGEN
CSIO1
CSIO2
Table 4-12 Chip Select Control Parameter Summary
Enable
Valid
Polarity
Size
Start Address
Stretch
Enable
Valid
Polarity
Size
Start Address
Stretch
Enable
Valid
Polarity
Size
Start Address
Stretch
Priority
Enable
Valid
Polarity
Size
Start Address
Stretch
Freescale Semiconductor, Inc.
OPERATING MODES AND ON-CHIP MEMORY
For More Information On This Product,
Go to: www.freescale.com
IO1EN in CSCTL —
IO1AV in CSGSIZ —
IO1PL in CSCTL —
Fixed —
$x060 —
IO1SA–IO1SB in CSSTRH — 0, 1, 2, or 3 E clocks
IO2EN in CSCTL —
IO2AV in CSGSIZ —
IO2PL in CSCTL —
Fixed —
$x800 —
IO2SA–IO2SB in CSSTRH — 0, 1, 2, or 3 E clocks
PCSEN in CSCTL —
Fixed (Address valid)
Fixed (Active low)
PSIZA–PSIZB —
Fixed (determined by size)
PSTHA–PSTHB in CSSTRH — 0, 1, 2, or 3 E clocks
GCSPR in CSCTL —
Set size to 0K to disable —
GAVLD in CSGSIZ —
GNPOL in CSGSIZ —
GSIZA–GSIZC in CSGSIZ — Refer to Table 4–12
GA[15:10] in CSGADR
GSTHA–GSTHB in CSSTRH — 0, 1, 2, or 3 E clocks
in CSCTL
1 = On, off at reset (0)
1 = Address valid, 0 = E valid
1 = Active high, 0 = Active low
($x060–$x7FF)
“x” is determined by REG[3:0] in INIT
1 = On, off at reset (0)
1 = Address valid, 0 = E valid
1 = Active high, 0 = Active low
($x800–$xFFF)
“x” is determined by REG[3:0] in INIT
1 = On, on after reset in expanded modes
0:0 = 64K ($0000–$FFFF)
0:1 = 32K ($8000–$FFFF)
1:0 = 16K ($C000–$FFFF)
1:1 = 8K ($E000–$FFFF)
1 cycle after reset in expanded mode
no delay after reset in all other modes
1 = CSGEN above CSPROG
0 = CSPROG above CSGEN
1 = CSGEN above CSPROG
0 = CSPROG above CSGEN
Address valid or E valid
Active high or low
off after reset in single-chip modes
4-23