DF2315VTE25 Renesas Electronics America, DF2315VTE25 Datasheet - Page 423
DF2315VTE25
Manufacturer Part Number
DF2315VTE25
Description
MCU 3V 384K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2315VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
DF2315VTE25V
Manufacturer:
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Quantity:
10 000
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Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-
count in the T
precedence and the TCFV/TCFU flag in TSR is not set.
Figure 9.57 shows the operation timing when there is contention between TCNT write and
overflow.
Multiplexing of I/O Pins: In the chip, the TCLKA input pin is multiplexed with the TIOCC0 I/O
pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O
pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input,
compare match output should not be performed from a multiplexed pin.
Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
φ
Address
Write signal
TCNT
TCFV flag
2
state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes
Figure 9.57 Contention between TCNT Write and Overflow
H'FFFF
Prohibited
TCNT write cycle
T
TCNT address
1
Rev.7.00 Feb. 14, 2007 page 389 of 1108
T
2
Section 9 16-Bit Timer Pulse Unit (TPU)
M
TCNT write data
REJ09B0089-0700
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