R5F21237JFP#U0 Renesas Electronics America, R5F21237JFP#U0 Datasheet - Page 355
R5F21237JFP#U0
Manufacturer Part Number
R5F21237JFP#U0
Description
IC R8C/23 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21237JFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21237JFP#U0R5F21237JFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21237JFP#U0R5F21237JFP#ES
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21237JFP#U0R5F21237JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
16.3.2
Table 16.7
STIE, NAKIE, RIE, TEIE, TIE: Bits in ICIER register
AL, STOP, NACKF, RDRF, TEND, TDRE: Bits in ICSR register
Transmit Data Empty
Transmit Ends
Receive Data Full
Stop Condition Detection
NACK Detection
Arbitration Lost / Overrun Error
The interrupt request of the I
the clock synchronous serial format is used.
Table 16.7 lists the Interrupt Requests of I
Since these interrupt requests are allocated at the I
by each bit is necessary.
When the generation conditions on the Table 16.7 are met, the I
Set the interrupt generation conditions to 0 by the I
TEND bits are automatically set to 0 by writing transmit data to the ICDRT register and the RDRF bit is
automatically set to 0 by reading the ICDRR register. When writing transmit data to the ICDRT register, the
TDRE bit is set to 0. When data is transferred from the ICDRT to ICDRS registers, the TDRE bit is set to 1 and
when further setting the TDRE bit to 0, extra 1 byte may be transmitted.
Also, set the STIE bit to 1 (enable stop condition detection interrupt request) when the STOP bit is set to 0.
Interrupt Requests
Interrupt Request
Interrupt Requests of I
Page 333 of 501
2
C bus interface contains 6 types when the I
NAKI
STPI
RXI
TXI
TEI
2
C Bus Interface
2
C Bus Interface.
TIE = 1 and TDRE = 1
TEIE = 1 and TEND = 1
RIE = 1 and RDRF = 1
STIE = 1 and STOP = 1
NAKIE = 1 and AL = 1 (or
NAKIE = 1 and NACKF = 1)
Generation Condition
2
C bus interface interrupt vector table, determining the source
2
C bus interface interrupt routine. However, the TDRE and
2
C bus interface interrupt request is generated.
16. Clock Synchronous Serial Interface
2
C bus format is used and 4 types when
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
I
2
C bus
Format
Synchronous
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Clock
Serial
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