MC9S12XA512VAG Freescale Semiconductor, MC9S12XA512VAG Datasheet - Page 1027

• Manufacturer Part Number: MC9S12XA512VAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA512VAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 24 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Port
AD1
J
1. Each cell represents one register with individual configuration bits
24.0.6
24.0.6.1
This register holds the value driven out to the pin if the pin is used as a general purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general purpose output.
When reading this address, the buffered state of the pin is returned if the associated data direction
register bit is set to “0”.
If the data direction register bits are set to logic level “1”, the contents of the data register is
returned. This is independent of any other configuration
24.0.6.2
This is a read-only register and always returns the buffered state of the pin
24.0.6.3
This register defines whether the pin is used as an input or an output.
If a peripheral module controls the pin the contents of the data direction register is ignored
(Figure
Data
yes
yes
24-68).
Registers
Data Register
Input Register
Data Direction Register
Direction
Data
yes
yes
Figure 24-68. Illustration of I/O Pin Functionality
Module
Table 24-60. Register Availability per Port
Input
yes
DDR
—
PTI
PT
module enable
data out
output enable
Reduced
Drive
0
1
yes
yes
0
1
0
1
Enable
Pull
yes
yes
(Figure
Polarity
Select
yes
—
24-68).
1
PIN
Wired-OR
Mode
—
—
(Figure
Interrupt
Enable
24-68).
yes
—
Interrupt
Flag
yes
—