MC9S12XD256VAG Freescale Semiconductor, MC9S12XD256VAG Datasheet - Page 400
MC9S12XD256VAG
Manufacturer Part Number
MC9S12XD256VAG
Description
IC MCU 256K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of MC9S12XD256VAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
14K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of
tap2tap column in
to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.
IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the
The equation used to generate the divider values from the IBFD bits is:
400
SCL
SDA
SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)}
SDA
SCL
START condition
Table
Table
9-3. The SCL Tap is used to generated the SCL period and the SDA Tap is used
9-3, all subsequent tap points are separated by 2
Figure 9-5. SCL Divider and SDA Hold
MC9S12XDP512 Data Sheet, Rev. 2.21
SCL Hold(start)
Table 9-4. Multiplier Factor
IBC7-6
00
01
10
11
SCL Divider
RESERVED
MUL
01
02
04
STOP condition
SDA Hold
IBC5-3
Table
Freescale Semiconductor
as shown in the
SCL Hold(stop)
9-4.
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