MC9S12XD256VAG Freescale Semiconductor, MC9S12XD256VAG Datasheet - Page 413
MC9S12XD256VAG
Manufacturer Part Number
MC9S12XD256VAG
Description
IC MCU 256K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of MC9S12XD256VAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
14K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9.5
The reset state of each individual bit is listed in
details the registers and their bit-fields.
9.6
IICV2 uses only one interrupt vector.
Internally there are three types of interrupts in IIC. The interrupt service routine can determine the interrupt
type by reading the status register.
IIC Interrupt can be generated on
The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to
the IBF bit in the interrupt service routine.
9.7
9.7.1
9.7.1.1
Reset will put the IIC bus control register to its default status. Before the interface can be used to transfer
serial data, an initialization procedure must be carried out, as follows:
Freescale Semiconductor
1. Arbitration lost condition (IBAL bit set)
2. Byte transfer condition (TCF bit set)
3. Address detect condition (IAAS bit set)
1. Update the frequency divider register (IBFD) and select the required division ratio to obtain SCL
2. Update the IIC bus address register (IBAD) to define its slave address.
3. Set the IBEN bit of the IIC bus control register (IBCR) to enable the IIC interface system.
4. Modify the bits of the IIC bus control register (IBCR) to select master/slave mode, transmit/receive
frequency from system clock.
mode and interrupt enable or not.
Interrupt
Interrupt
Resets
Interrupts
Initialization/Application Information
IIC
IIC Programming Examples
Initialization Sequence
Offset
—
Vector
—
MC9S12XDP512 Data Sheet, Rev. 2.21
Priority
Table 9-8. Interrupt Summary
—
IBAL, TCF, IAAS
Section 9.3, “Memory Map and Register
bits in IBSR
Source
register
Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
When either of IBAL, TCF or IAAS bits is set
may cause an interrupt based on arbitration
lost, transfer complete or address detect
conditions
Description
Definition,” which
413
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