R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1004

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 Controller Area Network (RCAN-TL1)
• MBIMR0
Bits 15 to 0 — Enable or disable interrupt requests from individual Mailbox-15 to Mailbox-0
respectively.
(8)
This register is a 32-bit read/conditionally write register and it records the mailboxes whose
contents have not been accessed by the CPU prior to a new message being received. If the CPU
has not cleared the corresponding bit in the RXPR or RFPR when a new message for that mailbox
is received, the corresponding UMSR bit is set to ‘1’. This bit may be cleared by writing a ‘1’ to
the corresponding bit location in the UMSR. Writing a ‘0’ has no effect.
If a mailbox is configured as transmit box, the corresponding UMSR will not be set.
• UMSR1
Note: * Only when writing a ‘1’ to clear.
Rev. 3.00 Sep. 28, 2009 Page 972 of 1650
REJ09B0313-0300
Bit[15:0]: MBIMR1 Description
0
1
Bit[15:0]: MBIMR0 Description
0
1
Initial value:
Initial value:
Unread Message Status Register (UMSR)
R/W:
R/W:
Bit:
Bit:
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
R/W
15
15
1
0
R/W
14
14
1
0
Interrupt Request from IRR1/IRR2/IRR8/IRR9 enabled
Interrupt Request from IRR1/IRR2/IRR8/IRR9 disabled (initial value)
Interrupt Request from IRR1/IRR2/IRR8/IRR9 enabled
Interrupt Request from IRR1/IRR2/IRR8/IRR9 disabled (initial value)
R/W
13
13
1
0
R/W
12
12
1
0
R/W
11
11
1
0
R/W
10
10
1
0
R/W
9
1
9
0
MBIMR0[15:0]
R/W
UMSR1[15:0]
8
1
8
0
R/W
7
1
7
0
R/W
6
0
6
1
R/W
5
0
5
1
R/W
4
1
4
0
R/W
3
0
3
1
R/W
2
0
2
1
R/W
1
0
1
1
R/W
0
0
0
1