R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1014

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 Controller Area Network (RCAN-TL1)
(5)
This register is a 6-bit read/write register. Its purpose is to store the number of the basic cycle for
Time -Triggered Transmissions. Its value is updated in different fashions depending if RCAN-TL1
is programmed to work as a potential time master or as a time slave. If RCAN-TL1 is working as
(potential) time master, CCR is:
If RCAN-TL1 is working as a time slave, CCR is only overwritten with the value of
MSG_DATA_0[5:0] of Mailbox 31 when a valid reference message is received.
If CMAX = 3'111, CCR is always H'0000.
• CCR (Address = H'08A)
Bits 15 to 6: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bits 5 to 0 — Cycle Counter Register (CCR): Indicates the number of the current Base Cycle of
the matrix cycle for Timer Triggered transmission.
Rev. 3.00 Sep. 28, 2009 Page 982 of 1650
REJ09B0313-0300
Bit0: TSR0
0
1
Initial value:
⎯ Incremented by one every time the cycle time (CYCTR) matches to Tx-Trigger Time of
⎯ Overwritten with the value contained in MSG_DATA_0[5:0] of Mailbox 31 when a valid
Cycle Counter Register (CCR)
R/W:
Mailbox-30 or
reference message is received.
Bit:
15
R
0
-
14
R
0
-
Description
Timer (TCNTR) has not overrun in event-trigger mode (Initial value)
Time reference message with Next_is_Gap has not been received in time-
trigger mode message error has not occurred in test mode.
[Clearing condition] Writing ‘1’ to IRR13
[Setting condition]
Timer (TCNTR) has overrun and changed from H'FFFF to H'0000 in event-
trigger mode.time reference message with Next_is_Gap has been received
in time-trigger mode message error has occurred in test mode
13
R
0
-
12
R
0
-
11
R
0
-
10
R
0
-
R
9
0
-
R
8
0
-
R
7
0
-
R
6
0
-
R/W
5
0
R/W
4
0
R/W
3
0
CCR[5:0]
R/W
2
0
R/W
1
0
R/W
0
0