R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1016

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 Controller Area Network (RCAN-TL1)
(8)
This register is a 16-bit read-only register. The purpose of this register is to capture Local Time
(TCNTR) at SOF of the reference message when the message is received or transmitted
successfully. In ET mode this register is not used and it is always cleared to zero.
• RFMK (Address = H'094)
Bits 15 to 0 — Reference Mark Register (RFMK): Indicates the value of TCNTR at SOF of
time reference message.
(9)
These three registers are 16-bit read/write registers and are capable of generating interrupt signals,
clearing-setting the Timer value (only supported by TCMR0) or clear the transmission messages
in the queue (only supported by TCMR2). TCMR0 is compared with TCNTR, however, TCMR1
and TCMR2 are compared with CYCTR.
The value used for the compare can be configured independently for each register. In order to set
flags, TTCR0 bit 12-10 needs to be set.
In Time-Trigger mode, TTCR0 bit6 has to be cleared by software to prevent TCNTR from being
cleared.
TMCR0 is for Init_Watch_Trigger, and TCMR2 is for Watch_Trigger.
Interrupt:
The interrupts are flagged by the Bit11, Bit15 and 14 in the IRR accordingly when a Compare
Match occurs, and setting these bits can be enabled by Bit12, Bit11, Bit10 in TTCR0. The
generation of interrupt signals itself can be prevented by the Bit11, Bit15 and Bit14 in the IMR.
When a Compare Match occurs and the IRR11 (or IRR15 or IRR14) is set, the Bit3 or Bit2 or Bit1
in the TSR (Timer Status Register) is also set. Clearing the IRR bit also clears the corresponding
bit of TSR.
Rev. 3.00 Sep. 28, 2009 Page 984 of 1650
REJ09B0313-0300
Initial value:
Reference Mark Register (RFMK)
Timer Compare Match Registers (TCMR0, TCMR1, TCMR2)
R/W:
Bit:
15
R
0
14
R
0
13
R
0
12
R
0
11
R
0
10
R
0
R
9
0
RFMK[15:0]
R
8
0
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0