R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1046

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Section 19 Controller Area Network (RCAN-TL1)
19.6
The DMAC can be activated by the reception of a message in RCAN-TL1 mailbox 0. When
DMAC transfer ends after DMAC activation has been set, flags of RXPR0 and RFPR0 are cleared
automatically. An interrupt request due to a receive interrupt from the RCAN-TL1 cannot be sent
to the CPU in this case. Figure 19.26 shows a DMAC transfer flowchart.
Rev. 3.00 Sep. 28, 2009 Page 1014 of 1650
REJ09B0313-0300
DMAC Interface
DMAC initialization
Message reception in RCAN-TL1
DMAC enable register setting
RXPR and RFPR flags clearing
End of DMAC transfer?
DMAC register information setting
Transfer counter = 0
Figure 19.26 DMAC Transfer Flowchart
DMAC activation
Interrupt to CPU
or DISEL = 1?
mailbox 0
END
Yes
Yes
No
No
: Settings by user
: Processing by hardware

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