R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1128

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 22 AND/NAND Flash Memory Controller (FLCTL)
22.6
The FLCTL can request DMA transfers separately to the data area FLDTFIFO and control code
area FLECFIFO. Table 22.6 summarizes DMA transfer enable or disable states in each access
mode.
Table 22.6 DMA Transfer Specifications
In little endian form, these bits should not be used because a 16-byte DMA transfer causes a data
replacement in longword units.
For details on DMAC settings, see section 10, Direct Memory Access Controller (DMAC).
22.7
(1)
When using the SNAND bit in FLCMNCR, only the first command or the second command is
corresponded in spite of the setting of the DOCMD1 or DOCMD2 bit in FLCMDCR. When no
command or only the first command is issued, 0 should be written in the SNAND bit.
Rev. 3.00 Sep. 28, 2009 Page 1096 of 1650
REJ09B0313-0300
FLDTFIFO
FLECFIFO
Usage Notes for the SNAND bit
DMA Transfer Specifications
Usage Notes
Sector Access Mode
DMA transfer enabled
DMA transfer enabled
Command Access Mode
DMA transfer enabled
DMA transfer disabled