R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1138

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 USB 2.0 Host/Function Module (USB)
Note:
Table 23.3 USB Data Bus Line Status
[Legend]
Chirp:
Squelch:
Not squelch: High-speed J state or high-speed K state
Chirp J:
Chirp K:
Rev. 3.00 Sep. 28, 2009 Page 1106 of 1650
REJ09B0313-0300
Bit
1, 0
LNST[1]
0
0
1
1
* Depending on the D+ and D− line status.
Bit Name
LNST[1:0]
The reset handshake protocol is being executed in high-speed operation enabled
state (the HSE bit in SYSCFG is set to 1).
SE0 or idle state
Chirp J state
Chirp K state
LNST[0]
0
1
0
1
Initial
Value
*
During Full-Speed
Operation
SE0
J state
K state
SE1
R/W
R
Description
USB Data Line Status
Table 23.3 shows the USB data bus line status. The
line status (D+ and D− lines) of the USB data bus is
monitored using the setting of these bits.
The line status can be confirmed with the full-speed
receiver. This module automatically controls the full-
speed receiver by supplying USBCLK. However, the
full-speed receiver can be enabled using software,
without supplying USBCLK, by setting the FSRPC bit
in SYSCFG. After a power-on reset, D+ and D− line
status can be confirmed prior to the USBCLK supply
by setting the FSRPC bit to 1.
Once USBCLK is supplied, software setting is not
required.
During High-Speed
Operation
Squelch
Not squelch
Invalid
Invalid
During Chirp
Operation
Squelch
Chirp J
Chirp K
Invalid