R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1153
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
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Part Number:
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Notes: 1. Only reading 0 and writing 1 are valid.
23.3.8
CFIFOCTR, D0FIFOCTR and D1FIFOCTR are registers that determine whether or not writing to
the buffer memory has been finished, the buffer in the CPU has been cleared, and the FIFO port is
accessible. CFIFOCTR, D0FIFOCTR, and D1FIFOCTR are used for the corresponding FIFO
ports.
These registers are initialized by a power-on reset or a software reset.
Initial value:
Bit
7
6 to 3
2 to 0
R/W:
Bit:
2. Changing the values of the CURPIPE bits in succession requires an access cycle
R/W*
BVAL
FIFO Port Control Registers (CFIFOCTR, D0FIFOCTR, D1FIFOCTR)
Bit Name
DEZPM
⎯
CURPIPE[2:0] 000
15
0
lasting a minimum of 120 ns plus five bus cycles.
1
BCLR
R/W*
14
0
2
FRDY
13
R
0
Initial
Value
0
All 0
12
R
0
-
11
R
0
R/W
R/W
R/W
R/W
10
R
0
R
9
0
Description
Zero-Length Packet Added Mode
This bit is valid when the transmitting direction
(reading from the buffer memory) has been set for
the pipe specified by the CURPIPE bits.
0: No packet is added.
1: A packet is added.
Reserved
These bits are always read as 0. The write value
should always be 0.
FIFO Port Access Pipe Specification*
000: Not specified
001: PIPE1
010 PIPE2
011: PIPE3
100: PIPE4
101: PIPE5
110: PIPE6
111: PIPE7
R
8
0
Section 23 USB 2.0 Host/Function Module (USB)
R
7
0
Rev. 3.00 Sep. 28, 2009 Page 1121 of 1650
DTLN[11:0]
R
6
0
R
5
0
R
4
0
R
3
0
REJ09B0313-0300
2
R
2
0
R
1
0
R
0
0
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