R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1157
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Part Number:
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23.3.11 Interrupts Enable Register 0 (INTENB0)
INTENB0 is a register that specifies the interrupt masks. The URST, SADR, SCFG and SUSP bits
operate as interrupt mask bits for the device state transition interrupt sources. The WDST, RDST,
CMPL and SERR bits operate as interrupt mask bits for the control transfer stage interrupt
sources.
This register is initialized by a power-on reset or a software reset.
Initial value:
Bit
15
14
13
12
11
10
R/W:
Bit:
VBSE
R/W
Bit Name
VBSE
RSME
SOFE
DVSE
CTRE
BEMPE
15
0
RSME SOFE
R/W
14
0
R/W
13
0
Initial
Value
0
0
0
0
0
0
DVSE
R/W
12
0
CTRE BEMPE NRDYE BRDYE URST
R/W
11
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
10
0
R/W
9
0
Description
VBUS Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
Resume Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
Frame Number Update Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
Device State Transition Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
Control Transfer Stage Transition Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
Buffer Empty Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
R/W
8
0
Section 23 USB 2.0 Host/Function Module (USB)
R/W
7
0
Rev. 3.00 Sep. 28, 2009 Page 1125 of 1650
SADR
R/W
6
0
SCFG
R/W
5
0
SUSP WDST RDST
R/W
4
0
R/W
3
0
REJ09B0313-0300
R/W
2
0
CMPL
R/W
1
0
SERR
R/W
0
0
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