R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1158

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 USB 2.0 Host/Function Module (USB)
Rev. 3.00 Sep. 28, 2009 Page 1126 of 1650
REJ09B0313-0300
Bit
9
8
7
6
5
4
3
Bit Name
NRDYE
BRDYE
URST
SADR
SCFG
SUSP
WDST
Initial
Value
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Buffer Not Ready Response Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
Buffer Ready Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
Default State Transition Notifications Enable
0: DVST interrupt disabled at transition to default
1: DVST interrupt enabled at transition to default
Address State Transition Notifications Enable
0: DVST interrupt disabled at transition to address
1: DVST interrupt enabled at transition to address
Configuration State Transition Notifications Enable
0: DVST interrupt disabled at transition to
1: DVST interrupt enabled at transition to
Suspend State Transition Notifications Enable
0: DVST interrupt disabled at transition to suspended
1: DVST interrupt enabled at transition to suspended
Control Write Stage Transition Notifications Enable
0: CTRT interrupt disabled at transition to control
1: CTRT interrupt enabled at transition to control
state
state
state
state
configuration state
configuration state
state
state
write stage
write stage