R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1188

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 USB 2.0 Host/Function Module (USB)
23.3.30 DCP Control Register (DCPCTR)
DCPCTR is a register that is used to confirm the buffer memory status, change and confirm the
data PID sequence bit, and set the response PID for the DCP.
This register is initialized by a power-on reset or a software reset. The CCPL and PID[2:0] bits are
initialized by a USB bus reset.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 1156 of 1650
REJ09B0313-0300
Bit
15
14
13 to 9
8
7
R/W:
Bit:
BSTS SUREQ
Bit Name
BSTS
SUREQ
⎯
SQCLR
SQSET
15
R
0
R/W*
14
0
2
13
R
0
-
12
Initial
Value
0
0
All 0
0
0
R
0
-
11
R
0
-
R/W
R
R/W*
R
R*
R*
10
R
0
-
1
1
/W*
/W*
2
2
2
R
9
0
-
Description
Buffer Status
0: Buffer access is disabled
1: Buffer access is enabled
The direction of buffer access, writing or reading,
depends on the ISEL bit in CFIFOSEL.
SETUP Token Transmission
Transmits the setup packet by setting this bit to 1.
This module clears this bit when the setup
transaction is completed. While this bit is 1,
USBREQ, USBVAL, USBINDX and USBLENG
should not be written to.
0: Invalid
1: Transmits the setup packet
Reserved
These bits are always read as 0. The write value
should always be 0.
Toggle Bit Clear*
0: Invalid
1: Specifies DATA0
Toggle Bit Set*
0: Invalid
1: Specifies DATA1
SQCLR SQSET SQMON
R*
W*
8
0
1
2
/
R*
W*
7
0
1
2
/
R
6
1
3
*
4
3
*
4
R
5
0
-
R
4
0
-
R
3
0
-
CCPL
R/W
2
0
R/W
1
0
PID[1:0]
R/W
0
0