R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1199

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

23.3.36 PIPEn Control Registers (PIPEnCTR) (n = 1 to 7)
PIPEnCTR is a register that is used to confirm the buffer memory status for the corresponding
pipe, change and confirm the data PID sequence bit, determine whether the auto response mode is
set, determine whether the auto buffer clear mode is set, and set a response PID. This register can
be set regardless of the pipe selection in PIPESEL.
This register is initialized by a power-on reset or a software reset. PID[1:0] are initialized by a
USB bus reset.
Initial value:
Bit
15
14
13 to 11 ⎯
10
R/W:
Bit:
BSTS INBUFM
Bit Name
BSTS
INBUFM
ATREPM
15
R
0
14
R
0
13
R
0
-
12
Initial
Value
0
0
All 0
0
R
0
-
11
R
0
-
R/W
R
R
R
R/W
REPM ACLRM SQCLR SQSET SQMON
R/W
10
AT
0
R/W R/W*
9
0
Description
Buffer Status
0: Buffer access is disabled
1: Buffer access is enabled
The direction of buffer access, writing or reading,
depends on setting of the DIR bit in PIPECFG. For
details, see section 23.4, Operation.
IN Buffer Monitor
This bit is valid when the corresponding pipe is set to
the transmitting direction.
0: There is no data to be transmitted in the buffer
1: There is data to be transmitted in the buffer
Note: This bit is valid for PIPE1 to PIPE5.
Reserved
These bits are always read as 0. The write value
should always be 0.
Auto Response Mode
0: Normal mode
1: Auto response mode
Note: This bit is valid for PIPE1 to PIPE5.
memory
memory
8
0
1
Section 23 USB 2.0 Host/Function Module (USB)
R/W*
7
0
1
Rev. 3.00 Sep. 28, 2009 Page 1167 of 1650
R
6
0
R
5
0
-
R
4
0
-
R
3
0
-
REJ09B0313-0300
R
2
0
-
R/W
1
0
PID[1:0]
R/W
0
0