R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1211

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Note:
If a zero-length packet has been received, the corresponding bit in BRDYSTS is set to 1 but data
in the corresponding packet cannot be read. The buffer should be cleared (BCLR = 1) after
clearing BRDYSTS.
With PIPE1 to PIPE7, if DMA transfer is performed in the reading direction, interrupts can be
generated in transfer units, by setting the BFRE bit in PIPECFG to 1.
Access
Direction
Write
* In non-continuous transfer (CNTMD = 0), “buffer full” means that the maximum packet
size of data has been received. In continuous transfer (CNTMD = 1), it means that the
buffer size of data has been received.
Transfer
Direction Pipe
Transmit
1 to 7
BFRE DBLB
0
1
1
Don't
care
Conditions under which BRDY Interrupts are
Generated
(1), (2), (3), (4) or (5) below:
(1) Software changes the direction of transfer
(2) Data is enabled to be transmitted by one of
(3) Transmission of data from one buffer is
(4) Software sets the ACLRM bit to 1 when
(5) Software sets the SCLR bit to 1 when there
Not generated
direction from receiving to transmitting.
(a) to (c) below, when there is no data
waiting to be transmitted in buffer:
(a) Buffer becomes full by writing data n
(b) Software sets the BVAL bit in
(c) Writing is completed in DMA transfer.
complete when there are data waiting to be
transmitted in both buffers
there are data waiting to be transmitted in
both buffers.
are data waiting to be transmitted in both
buffers.
Section 23 USB 2.0 Host/Function Module (USB)
times the maximum packet size (n = 1
during a non-continuous transfer).
DnFIFOCTR to 1 to enable the buffer to
transmit data.
Rev. 3.00 Sep. 28, 2009 Page 1179 of 1650
REJ09B0313-0300