R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1265

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

A unified memory architecture is adopted for the LCD controller (LCDC) so that the image data
for display is stored in system memory. The LCDC module reads data from system memory, uses
the palette memory to determine the colors, then puts the display on the LCD panel. It is possible
to connect the LCDC to the LCD module* other than microcomputer bus interface types and
NTSC/PAL types and those that apply the LVDS interface.
Note: * LCD module can be connected to the LVDS interface by using the LSI with LVDS
24.1
The LCDC has the following features.
• Panel interface
• Supports 4/8/15/16-bpp (bits per pixel) color modes
• Supports 1/2/4/6-bpp grayscale modes
• Supports LCD-panel sizes from 16 × 1 to 1024 × 1024*
• 24-bit color palette memory (16 of the 24 bits are valid; R:5/G:6/B:5)
• STN/DSTN panels are prone to flicker and shadowing. The controller applies 65536-color
• Dedicated display memory is unnecessary using part of the synchronous DRAM (area 3) as the
• The display is stable because of the large 2.4-kbyte line buffer
• Supports the inversion of the output signal to suit the LCD panel's signal polarity
• Supports the selection of data formats (the endian setting for bytes, backed pixel method) by
• An interrupt can be generated at the user specified position (controlling the timing of VRAM
• A hardware-rotation mode is included to support the use of landscape-format LCD panels as
Notes: 1. When connecting the LCDC to a TFT panel with an unwired 18-bit bus, the lower bit
⎯ Serial interface method
⎯ Supports data formats for STN/dual-STN/TFT panels (8/12/16/18-bit bus width)*
control by 24-bit space-modulation FRC with 8-bit RGB values for reduced flicker.
VRAM to store display data of the LCDC.
register settings
update start prevents flicker)
portrait-format LCD panels (the horizontal width of the panel before rotation must be within
320 pixels (see table 24.5.)
2. For details, see section 24.4.1, LCD Module Sizes which can be Displayed in this
Features
conversion LSI.
lines should be connected to GND or to the lowest bit from which data is output.
LCDC.
Section 24 LCD Controller (LCDC)
Rev. 3.00 Sep. 28, 2009 Page 1233 of 1650
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Section 24 LCD Controller (LCDC)
REJ09B0313-0300
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