R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1269

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

24.3.1
This LCDC can select bus clock, the peripheral clock, or the external clock as its operation clock
source. The selected clock source can be divided using an internal divider into a clock of 1/1 to
1/32 and be used as the LCDC operating clock (DOTCLK). The clock output from the LCDC is
used to generate the synchronous clock output (LCD_CL2) for the LCD panel from the operating
clock selected in this register. For a TFT panel, LCD_CL2 = DOTCLK, and for an STN or DSTN
panel, LCD_CL2 = a clock with a frequency of (DOTCLK/data bus width of output to LCD
panel). The LDICKR must be set so that the clock input to the LCDC is 66 MHz or less regardless
of the LCD_CL2.
Initial value:
Bit
15, 14
Register Name
LCDC power supply sequence
period register
LCDC control register
LCDC user specified interrupt
control register
LCDC user specified interrupt
line number register
LCDC memory access interval
number register
R/W:
Bit:
LCDC Input Clock Register (LDICKR)
15
R
0
Bit Name
⎯
-
14
R
0
-
R/W
ICKSEL[1:0]
13
0
Initial
Value
All 0
R/W
12
0
11
Abbreviation
LDPSPR
LDCNTR
LDUINTR
LDUINTLNR
LDLIRNR
R
0
-
R/W
R
10
R
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
R
9
0
-
R/W
R/W
R/W
R/W
R/W
R/W
R
8
1
-
R
7
0
-
Initial Value
H'F60F
H'0000
H'0000
H'004F
H'0000
Rev. 3.00 Sep. 28, 2009 Page 1237 of 1650
R
6
0
-
R/W
5
0
Section 24 LCD Controller (LCDC)
R/W
Address
H'FFFFFC26
H'FFFFFC28
H'FFFFFC34
H'FFFFFC36
H'FFFFFC40
4
0
R/W
DCDR[5:0]
3
0
REJ09B0313-0300
R/W
2
0
R/W
Access
Size
16
16
16
16
16
1
0
R/W
0
1