R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1272
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
Company:
Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
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Section 24 LCD Controller (LCDC)
Rev. 3.00 Sep. 28, 2009 Page 1240 of 1650
REJ09B0313-0300
Bit
10
9
8
7, 6
Bit Name
MCNT
CL1CNT
CL2CNT
⎯
Initial
Value
0
0
1
All 0
R/W
R/W
R/W
R/W
R
Description
M Signal Control
Sets whether or not to output the LCD's current-
alternating signal of the LCD module.
0: M (AC line modulation) signal is output
1: M signal is not output
CL1 (Horizontal Sync Signal) Control
Sets whether or not to enable CL1 output during the
vertical retrace period.
0: CL1 is output during vertical retrace period
1: CL1 is not output during vertical retrace period
CL2 (Dot Clock of LCD Module) Control
Sets whether or not to enable CL2 output during the
vertical and horizontal retrace period.
0: CL2 is output during vertical and horizontal retrace
1: CL2 is not output during vertical and horizontal
Reserved
These bits are always read as 0. The write value
should always be 0.
period
retrace period
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