R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1341

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Notes: 1. In 8-bit access, the register can be read but cannot be written to.
25.2.1
PBIORL is a 16-bit readable/writable register that is used to set the pins on port B as inputs or
outputs. The PB11IOR to PB8IOR bits correspond to the PB11/CTx1 to PB8/CRx0/ CRx0/CRx1
pins, respectively. PBIORL is enabled when the port B pins are functioning as general-purpose
input/output (PB11 to PB18). In other states, they are disabled. If a bit in PBIORL is set to 1, the
corresponding pin on port B functions as output. If it is cleared to 0, the corresponding pin
functions as input.
Bits 15 to 12 and bits 7 to 0 in PBIORL are reserved. These bits are always read as 0. The write
value should always be 0.
Initial value:
Port F control register H4
Port F control register H3
Port F control register H2
Port F control register H1
Port F control register L4
Port F control register L3
Port F control register L2
Port F control register L1
SSI oversampling clock selection
register
Register Name
R/W:
Bit:
2. The initial value depends on the operating mode of the LSI.
Port B I/O Register L (PBIORL)
15
R
0
-
14
R
0
-
13
R
0
-
12
R
0
-
PB11
R/W
IOR
11
0
PFCRH4
PFCRH3
PFCRH2
PFCRH1
SCSR
Abbreviation
PFCRL4
PFCRL3
PFCRL2
PFCRL1
PB10
R/W
IOR
10
0
R/W
PB9
IOR
9
0
R/W
PB8
IOR
8
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
7
0
-
Rev. 3.00 Sep. 28, 2009 Page 1309 of 1650
Initial
Value
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
Section 25 Pin Function Controller (PFC)
R
6
0
-
R
5
0
-
H'FFFE3A8A 8, 16
H'FFFE3A8E 8, 16
H'FFFE3A90
H'FFFE3A92
H'FFFE3A94
H'FFFE3A96
H'FFFE3AA2 8, 16
Address
H'FFFE3A88
H'FFFE3A8C 8, 16, 32
R
4
0
-
R
3
0
-
REJ09B0313-0300
R
2
0
-
8, 16, 32
8, 16, 32
8, 16
8, 16, 32
8, 16
Access
Size
R
1
0
-
R
0
0
-

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